HB52D168DC-F
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
20
SDRAM device attributes:
0
0
0
0
0
0
0
1
01
0
W latency
21
22
SDRAM module attributes
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
00
0E
Non buffer
VCC ± 10%
SDRAM device attributes:
General
23
SDRAM cycle time
(2nd highest CE latency)
(-A6F/A6FL) 10 ns
1
0
1
0
0
0
0
0
A0
CL = 2
(-B6F/B6FL) 15 ns
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
F0
60
24
SDRAM access from Clock
(2nd highest CE latency)
(-A6F/A6FL) 6 ns
CL = 2
(-B6F/B6FL) 9 ns
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
90
00
25
26
SDRAM cycle time
(3rd highest CE latency)
Undefined
SDRAM access from Clock
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
27
28
29
30
31
Minimum row precharge time
Row active to row active min
RE to CE delay min
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
14
14
14
32
10
20 ns
20 ns
20 ns
50 ns
Minimum RE pulse width
Density of each bank on
module
2 bank
64M byte
32
33
Address and command signal 0
input setup time
0
0
1
0
0
1
0
0
0
0
0
0
0
0
20
10
2 ns
1 ns
Address and command signal 0
input hold time
34
35
Data signal input setup time
Data signal input hold time
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
20
10
00
12
06
2 ns
1 ns
36 to 61 Superset information
Future use
Rev. 1.2A
6
62
63
SPD data revision code
Checksum for bytes 0 to 62
(-A6F/A6FL)
(-B6F/B6FL)
1
0
0
´
0
0
0
´
0
0
0
´
0
0
0
´
0
0
0
´
1
1
0
´
1
1
0
´
0
1
0
´
86
07
00
´ ´
134
64
Manufacturer’s JEDEC ID code
HITACHI
65 to 71 Manufacturer’s JEDEC ID code
72 Manufacturing location
*3 (ASCII-
8bit code)
7