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HB52D48GB-B6F PDF预览

HB52D48GB-B6F

更新时间: 2024-01-20 15:29:13
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器PC时钟
页数 文件大小 规格书
23页 139K
描述
32 MB Unbuffered SDRAM Micro DIMM 4-Mword × 64-bit, 100 MHz Memory Bus, 1-Bank Module (4 pcs of 4 M × 16 components) PC100 SDRAM

HB52D48GB-B6F 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM144,20针数:144
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.24风险等级:5.84
Is Samacsys:N访问模式:SINGLE BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):100 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N144长度:42 mm
内存密度:268435456 bit内存集成电路类型:SYNCHRONOUS DRAM MODULE
内存宽度:64功能数量:1
端口数量:1端子数量:144
字数:4194304 words字数代码:4000000
工作模式:SYNCHRONOUS最高工作温度:65 °C
最低工作温度:组织:4MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM144,20
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
电源:3.3 V认证状态:Not Qualified
刷新周期:4096座面最大高度:30 mm
自我刷新:YES最大待机电流:0.004 A
子类别:DRAMs最大压摆率:0.44 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL宽度:3.8 mm
Base Number Matches:1

HB52D48GB-B6F 数据手册

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HB52D48GB-F  
32 MB Unbuffered SDRAM Micro DIMM  
4-Mword × 64-bit, 100 MHz Memory Bus, 1-Bank Module  
(4 pcs of 4 M × 16 components)  
PC100 SDRAM  
E0011H10 (1st edition)  
(Previous ADE-203-1149A (Z))  
Jan. 19, 2001  
Description  
The HB52D48GB is a 4M × 64 × 1 banks Synchronous Dynamic RAM Micro Dual In-line Memory Module  
(Micro DIMM), mounted 4 pieces of 64-Mbit SDRAM (HM5264165FTT) sealed in TSOP packageand 1 piece  
of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the product is 144-pin Zig Zag  
Dual tabs socket type compact and thin package. Therefore, it makes high density mounting possible without  
surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted  
beside TSOP on the module board.  
Features  
144-pin Zig Zag Dual tabs socket type (dual lead out)  
Outline: 38.00 mm (Length) × 30.00 mm (Height) × 3.80 mm (Thickness)  
Lead pitch: 0.50 mm  
3.3 V power supply  
Clock frequency: 100 MHz (max)  
LVTTL interface  
Data bus width: × 64 Non parity  
Single pulsed RAS  
4 Banks can operates simultaneously and independently  
Burst read/write operation and burst read/single write operation capability  
Programmable burst length : 1/2/4/8/full page  
2 variations of burst sequence  
Sequential (BL = 1/2/4/8/full page)  
interleave (BL = 1/2/4/8)  
This Product became EOL in October, 2005.  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  

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