Symbol
Type
Function
Connectivity Test Mode Enable: Required on x16 devices and optional input on x4/x8
with densities equal to or greater than 8Gb. HIGH in this pin will enable Connectivity Test
TEN
Input Mode operation along with other pins. It is a CMOS rail to rail signal with AC high and
low at 80% and 20% of VDD. Using this signal or not is dependent on System. This pin
may be DRAM internally pulled low through a weak pull-down resistor to VSS.
NC
No Connect: No internal electrical connection is present.
Supply DQ Power Supply: 1.2 V +/- 0.06 V
Supply DQ Ground
VDDQ
VSSQ
VDD
Supply Power Supply: 1.2 V +/- 0.06 V
Supply Ground
VSS
Vpp
Supply DRAM Activation Power Supply: 2.5V (2.375V min , 2.75 max)
Supply Reference voltage for CA
VREFCA
ZQ
Supply Reference Pin for ZQ calibration
Note:
Input only pins (BG0-BG-1, BA0-BA1, A0-A17, ACT_n, RAS_n,/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and
RESET_n) do not supply termination.
Rev. 1.4 / Apr.2020
10