GS9090B GenLINX® III
270Mb/s Deserializer for SDI
GS9090B Data Sheet
Key Features
Description
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SMPTE 259M-C compliant descrambling and NRZI
to NRZ decoding (with bypass)
The GS9090B is a 270Mb/s reclocking deserializer with
an internal FIFO. It provides a complete receive solution
for SD-SDI and DVB-ASI applications.
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DVB-ASI sync word detection and 8b/10b decoding
Integrated line-based FIFO for data
In addition to reclocking and deserializing the input data
stream, the GS9090B performs NRZI-to-NRZ decoding,
descrambling as per SMPTE 259M-C, and word align-
ment when operating in SMPTE mode. When operating
in DVB-ASI mode, the device will word align the data to
K28.5 sync characters and 8b/10b decode the received
stream.
alignment/delay, clock phase interchange, DVB-ASI
data packet extraction and clock rate interchange,
and ancillary data packet extraction
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Integrated VCO and reclocker
Automatic or manual selection between SMPTE
video and DVB-ASI data
The internal reclocker features a very wide input jitter
tolerance, and is fully compatible with both SMPTE and
DVB-ASI input streams.
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User selectable additional processing features
including:
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TRS, ANC data checksum, and EDH CRC error
detection and correction
The GS9090B includes a range of data processing
functions such as EDH support (error detection and
handling), and automatic standards detection. The de-
vice can also detect and extract SMPTE 352M
payload identifier packets and independently identify
the received video standard. This information is read
from internal registers via the host interface port.
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programmable ANC data detection
illegal code remapping
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Internal flywheel for noise immune H, V, F
extraction
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Automatic standards detection and indication
Enhanced Gennum Serial Peripheral Interface
(GSPI)
The GS9090B also incorporates a video line-based
FIFO. This FIFO may be used in four user-selectable
modes to carry out tasks such as data alignment / delay,
clock phase interchange, MPEG packet extraction and
clock rate interchange, and ancillary data packet extrac-
tion.
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JTAG test interface
Polarity insensitive for DVB-ASI and SMPTE
signals
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+1.8V core power supply with optional +1.8V or
+3.3V I/O power supply
Parallel data outputs are provided in 10-bit multiplexed
format, with the associated parallel clock output signal
operating at 27MHz.
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Small footprint (8mm x 8mm)
Low power operation (typically 145mW)
Pb-free
The device may also be used in a low-latency data pass
through mode where only descrambling and word align-
ment will be performed in SMPTE mode.
Applications
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SMPTE 259M-C Serial Digital Interfaces
DVB-ASI Serial Digital Interfaces
40749 - 2 January 2007
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