5秒后页面跳转
捷配首页

Datasheet > GS88132BGT-200IT
GS88132BGT-200IT PDF预览

GS88132BGT-200IT

更新时间： 2024-11-26 06:54:51
品牌 Logo 应用领域
GSI 静态存储器
页数 文件大小 规格书
38页 1304K
描述
Cache SRAM, 256KX32, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

阅读下载

中文翻译

获取价格

GS88132BGT-200IT 数据手册

 浏览型号GS88132BGT-200IT的Datasheet PDF文件第2页浏览型号GS88132BGT-200IT的Datasheet PDF文件第3页浏览型号GS88132BGT-200IT的Datasheet PDF文件第4页浏览型号GS88132BGT-200IT的Datasheet PDF文件第5页浏览型号GS88132BGT-200IT的Datasheet PDF文件第6页浏览型号GS88132BGT-200IT的Datasheet PDF文件第7页 
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)  
333 MHz–150 MHz  
100-pin TQFP & 165-bump BGA  
Commercial Temp  
512K x 18, 256K x 32, 256K x 36  
2.5 V or 3.3 V V  
DD  
9Mb Sync Burst SRAMs  
2.5 V or 3.3 V I/O  
Industrial Temp  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by  
the user via the FT mode pin (Pin 14). Holding the FT mode  
pin low places the RAM in Flow Through mode, causing  
output data to bypass the Data Output Register. Holding FT  
high places the RAM in Pipeline mode, activating the rising-  
edge-triggered Data Output Register.  
Features  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP and 165-bump BGA  
packages  
• RoHS-compliant 100-lead TQFP and 165-bump BGA  
packages available  
SCD Pipelined Reads  
The GS88118B(T/D)/GS8813B(T/D)/GS88136B(T/D) is a  
SCD (Single Cycle Desepipelined synchronous SRAM.  
DCD (Dual Cycle Deselecversions are also available. SCD  
SRAMs pipeline deselect commands one stage less than read  
commands. SCD RAMs begin turning off their outputs  
immediately aftethe deselect command has been captured in  
the input registers.  
Functional Description  
Byte Write and Global Write  
Applications  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) is a  
9,437,184-bit high performance synchronous SRAM with a 2-  
bit burst address counter. Although of a type originally  
developed for Level 2 Cache applications supporting high  
performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main  
store to networking chip set support.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Controls  
Addresses, data I/Os, chip enable (E1, E2), address burst  
control inputs (ADSP, ADSC, ADV) and write control inputs  
(Bx, BW, GW) are synchronous and acontrolled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) arasynchronous inputs. Burst  
cycles can be initiated with her ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
counter may be confred to count in either linear or  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
Core and Interface Voltages  
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)  
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V  
and 2.5 V compatible. Separate output power (V  
) pins are  
DDQ  
used to decouple output noise from the internal circuits and are  
3.3 V and 2.5 V compatible.  
Paramter Synopsis  
-333  
-300  
-250  
-200  
-150  
Unit  
tKQ  
2.5  
3.0  
2.5  
3.3  
2.5  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
tCycle  
Pipeline  
3-1-1-1  
Curr (x18)  
Curr (x32/x36)  
250  
290  
230  
265  
200  
230  
170  
195  
140  
160  
mA  
mA  
tKQ  
4.5  
4.5  
5.0  
5.0  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
tCycle  
Flow Through  
2-1-1-1  
Curr (x18)  
Curr (x32/x36)  
200  
230  
185  
210  
160  
185  
140  
160  
128  
145  
mA  
mA  
Rev: 1.06a 2/2008  
1/38  
© 2002, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...38

中文翻译

下载PDF

与GS88132BGT-200IT相关器件

型号 品牌 获取价格 描述 数据表
GS88132BGT-200IV GSI

获取价格

 		512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88132BGT-200IVT GSI

获取价格

 		暂无描述
GS88132BGT-200V GSI

获取价格

 		512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88132BGT-250T GSI

获取价格

 		Cache SRAM, 256KX32, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS88132BGT-300 GSI

获取价格

 		512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88132BGT-300I GSI

获取价格

 		512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88132BGT-300IT GSI

获取价格

 		Cache SRAM, 256KX32, 5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS88132BGT-333I GSI

获取价格

 		Cache SRAM, 256KX32, 4.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS88132BGT-333T GSI

获取价格

 		Cache SRAM, 256KX32, 4.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS88132BT-150 GSI

获取价格

 		512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

与GS88132BGT-200IT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证