Datasheet > GS88118BGT-133I

GS88118BGT-133I

更新时间： 2024-11-27 09:28:31

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
36页	840K
描述
Cache SRAM, 512KX18, 8.5ns, CMOS, PQFP100, TQFP-100

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数据手册

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GS88118BGT-133I 数据手册

GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)

100-Pin TQFP & 165-bump BGA

Commercial Temp

Industrial Temp

250 MHz–133 MHz

512K x 18, 256K x 32, 256K x 36

9Mb Sync Burst SRAMs

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

internally and are controlled by ADV. The burst address

Features

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode pin

low places the RAM in Flow Through mode, causing output

data to bypass the Data Output Register. Holding FT high

places the RAM in Pipeline mode, activating the rising-edge-

triggered Data Output Register.

• Automatic power-down for portable applications

• JEDEC-standard packages

-250 -225 -200 -166 -150 -133 Unit

SCD Pipelined Reads

Pipeline

3-1-1-1

2.5 2.7 3.0 3.4 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.7 7.5 ns

The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) is a

SCD (Single Cycle Deselect) pipelined synchronous SRAM.

DCD (Dual Cycle Deselect) versions are also available. SCD

SRAMs pipeline deselect commands one stage less than read

commands. SCD RAMs begin turning off their outputs

immediately after the deselect command has been captured in

the input registers.

tCycle

Curr ^(x18)

280 255 230 200 185 165 mA

3.3 V

2.5 V

Curr (x32/x36) 330 300 270 230 215 190 mA

Curr ^(x18)275 250 230 195 180 165 mA

Curr ^(x32/x36)320 295 265 225 210 185 mA

Flow

Through

2-1-1-1

5.5 6.0 6.5 7.0 7.5 8.5 ns

tCycle

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Curr ^(x18)

175 165 160 150 145 135 mA

3.3 V

2.5 V

Curr (x32/x36) 200 190 180 170 165 150 mA

Curr ^(x18)175 165 160 150 145 135 mA

Curr ^(x32/x36)200 190 180 170 165 150 mA

Sleep Mode

Functional Description

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Applications

The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) is a

9,437,184-bit high performance synchronous SRAM with a 2-

bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Core and Interface Voltages

The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)

operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V

and 2.5 V compatible. Separate output power (V

) pins are

DDQ

used to decouple output noise from the internal circuits and are

3.3 V and 2.5 V compatible.

Controls

Addresses, data I/Os, chip enable (E1, E2), address burst

control inputs (ADSP, ADSC, ADV) and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

Rev: 1.01 8/2003

1/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).

12 3 4 5 6 7...36

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与GS88118BGT-133I相关器件

型号	品牌	获取价格	描述	数据表
GS88118BGT-150	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88118BGT-150I	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88118BGT-150IT	GSI	获取价格	Cache SRAM, 512KX18, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS88118BGT-150IV	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88118BGT-150T	GSI	获取价格	Cache SRAM, 512KX18, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS88118BGT-150V	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88118BGT-150VT	GSI	获取价格	Cache SRAM, 512KX18, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS88118BGT-166	GSI	获取价格	Cache SRAM, 512KX18, 7ns, CMOS, PQFP100, TQFP-100
GS88118BGT-166IT	GSI	获取价格	Cache SRAM, 512KX18, 7ns, CMOS, PQFP100, TQFP-100
GS88118BGT-200	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

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