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GS8662T38AGE-400T PDF预览

GS8662T38AGE-400T

更新时间: 2024-02-24 01:51:15
品牌 Logo 应用领域
GSI 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
31页 1057K
描述
DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS8662T38AGE-400T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:LBGA,针数:165
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.53
最长访问时间:0.45 nsJESD-30 代码:R-PBGA-B165
JESD-609代码:e1长度:17 mm
内存密度:75497472 bit内存集成电路类型:DDR SRAM
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:165
字数:2097152 words字数代码:2000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2MX36
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.5 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15 mm
Base Number Matches:1

GS8662T38AGE-400T 数据手册

 浏览型号GS8662T38AGE-400T的Datasheet PDF文件第2页浏览型号GS8662T38AGE-400T的Datasheet PDF文件第3页浏览型号GS8662T38AGE-400T的Datasheet PDF文件第4页浏览型号GS8662T38AGE-400T的Datasheet PDF文件第5页浏览型号GS8662T38AGE-400T的Datasheet PDF文件第6页浏览型号GS8662T38AGE-400T的Datasheet PDF文件第7页 
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
450 MHz–300 MHz  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
72Mb SigmaCIO DDR-II+  
Burst of 2 SRAM  
1.8 V V  
DD  
1.8 V and 1.5 V I/O  
Features  
• 2.5 Clock Latency  
• Simultaneous Read and Write SigmaCIO™ Interface  
• Common I/O bus  
• JEDEC-standard pinout and package  
• Double Data Rate interface  
• Byte Write (x36 and x18) and Nybble Write (x8) function  
• Burst of 2 Read and Write  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
• Pipelined read operation with self-timed Late Write  
• Fully coherent read and write pipelines  
• ZQ pin for programmable output drive strength  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• Pin-compatible with present 9Mb, 18Mb, 36Mb and future  
144Mb devices  
Bottom View  
165-Bump, 15 mm x 17 mm BGA  
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
1 mm Bump Pitch, 11 x 15 Bump Array  
SigmaCIOFamily Overview  
Clocking and Addressing Schemes  
The GS8662T20/38AE are built in compliance with the  
SigmaCIO DDR-II+ SRAM pinout standard for Common I/O  
synchronous SRAMs. They are 75,497,472-bit (72Mb)  
SRAMs. The GS8662T20/38AE SigmaCIO SRAMs are just  
one element in a family of low power, low voltage HSTL I/O  
SRAMs designed to operate at the speeds needed to implement  
economical high performance networking systems.  
The GS8662T20/38AE SigmaCIO DDR-II+ SRAMs are  
synchronous devices. They employ two input register clock  
inputs, K and K. K and K are independent single-ended clock  
inputs, not differential inputs to a single differential clock input  
buffer.  
Common I/O x36 and x18 SigmaCIO DDR-II+ B2RAMs  
always transfer data in two packets. When a new address is  
loaded, A0 presets an internal 1 bit address counter. The  
counter increments by 1 (toggles) for each beat of a burst of  
two data transfer.  
Common I/O x8 SigmaCIO DDR-II+ B2 RAMs always  
transfer data in two packets. When a new address is loaded,  
the LSB is internally set to 0 for the first read or write transfer,  
and incremented by 1 for the next transfer. Because the LSB  
is tied off internally, the address field of a x8 SigmaCIO DDR-  
II+ B4 RAM is always one address pin less than the advertised  
index depth (e.g., the 4M x 18 has a 2048K addressable index).  
Parameter Synopsis  
-450  
-400  
-375  
-333  
3.3 ns  
0.45 ns  
-300  
3.0 ns  
0.45 ns  
tKHKH  
tKHQV  
2.22 ns  
0.45 ns  
2.5 ns  
2.67 ns  
0.45 ns  
0.45 ns  
Rev: 1.00b 10/2009  
1/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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