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GS8322Z18B-V PDF预览

GS8322Z18B-V

更新时间: 2024-01-03 04:49:16
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GSI 静态存储器
页数 文件大小 规格书
39页 2087K
描述
36Mb Pipelined and Flow Through Synchronous NBT SRAM

GS8322Z18B-V 数据手册

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GS8322Z18/36/72(B/E/C)-xxxV  
250 MHz133 MHz  
119, 165 & 209 BGA  
Commercial Temp  
Industrial Temp  
36Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
Features  
Because it is a synchronous device, address, data inputs, and  
read/write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
• NBT (No Bus Turn Around) functionality allows zero wait  
Read-Write-Read bus utilization; fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 1.8 V or 2.5 V core power supply  
• 1.8 V or 2.5 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• ZQ mode pin for user-selectable high/low output drive  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• LBO pin for Linear or Interleave Burst mode  
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
• JEDEC-standard 119-, 165- or 209-Bump BGA package  
• RoHS-compliant packages available  
The GS8322Z18/36/72-xxxV may be configured by the user to  
operate in Pipeline or Flow Through mode. Operating as a  
pipelined synchronous device, in addition to the rising-edge-  
triggered registers that capture input signals, the device  
incorporates a rising edge triggered output register. For read  
cycles, pipelined SRAM output data is temporarily stored by  
the edge-triggered output register during the access cycle and  
then released to the output drivers at the next rising edge of  
clock.  
Functional Description  
The GS8322Z18/36/72-xxxV is a 36Mbit Synchronous Static  
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or  
other pipelined read/double late write or flow through read/  
single late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS8322Z18/36/72-xxxV is implemented with GSI's high  
performance CMOS technology and is available in a JEDEC-  
standard 119-bump, 165-bump or 209-bump BGA package.  
Parameter Synopsis  
-250 -225 -200 -166 -150 -133 Unit  
t
3.0 3.0 3.0 3.5 3.8 4.0 ns  
4.0 4.4 5.0 6.0 6.7 7.5 ns  
KQ  
tCycle  
Pipeline  
3-1-1-1  
Curr (x18)  
Curr (x36)  
Curr (x72)  
275 255 240 215 205 180 mA  
330 300 280 245 230 205 mA  
415 385 340 305 285 255 mA  
t
6.5 7.0 7.5 8.0 8.5 8.5 ns  
6.5 7.0 7.5 8.0 8.5 8.5 ns  
KQ  
Flow  
tCycle  
Through  
2-1-1-1  
Curr (x18)  
Curr (x36)  
Curr (x72)  
200 190 180 170 160 150 mA  
225 215 205 195 185 170 mA  
300 280 255 245 230 225 mA  
Rev: 1.05 6/2006  
1/39  
© 2002, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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