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GS832236AB-150IV PDF预览

GS832236AB-150IV

更新时间： 2024-11-23 14:33:47
品牌 Logo 应用领域
GSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
36页 526K
描述
Cache SRAM, 1MX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119

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GS832236AB-150IV 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：BGA, BGA119,7X17,50针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41Factory Lead Time：8 weeks
风险等级：5.1最长访问时间：7.5 ns
其他特性：ALSO OPERATES AT 2.5V SUPPLY, PIPELINED ARCHITECTURE, FLOW THROUGH最大时钟频率 (fCLK)：150 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：37748736 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端子数量：119字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.8/2.5 V
认证状态：Not Qualified座面最大高度：1.99 mm
最大待机电流：0.04 A最小待机电流：1.7 V
子类别：SRAMs最大压摆率：0.165 mA
最大供电电压 (Vsup)：2 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

GS832236AB-150IV 数据手册

 浏览型号GS832236AB-150IV的Datasheet PDF文件第2页浏览型号GS832236AB-150IV的Datasheet PDF文件第3页浏览型号GS832236AB-150IV的Datasheet PDF文件第4页浏览型号GS832236AB-150IV的Datasheet PDF文件第5页浏览型号GS832236AB-150IV的Datasheet PDF文件第6页浏览型号GS832236AB-150IV的Datasheet PDF文件第7页 
GS832218/36A(B/D)-xxxV  
119 & 165 BGA  
Commercial Temp  
Industrial Temp  
333 MHz–150 MHz  
2M x 18, 1M x 36  
36Mb S/DCD Sync Burst SRAMs  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
Flow Through/Pipeline Reads  
Features  
The function of the Data Output register can be controlled by the  
user via the FT mode . Holding the FT mode pin low places the  
RAM in Flow Through mode, causing output data to bypass the  
Data Output Register. Holding FT high places the RAM in  
Pipeline mode, activating the rising-edge-triggered Data Output  
Register.  
• FT pin for user-configurable flow through or pipeline operation  
• Single/Dual Cycle Deselect selectable  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• ZQ mode pin for user-selectable high/low output drive  
• 1.8 V or 2.5 V core power supply  
• 1.8 V or 2.5 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to SCD x18/x36 Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 119- and 165-bump BGA packages  
• RoHS-compliant packages available  
SCD and DCD Pipelined Reads  
The GS832218/36A-xxxV is a SCD (Single Cycle Deselect) and  
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD  
SRAMs pipeline disable commands to the same degree as read  
commands. SCD SRAMs pipeline deselect commands one stage  
less than read commands. SCD RAMs begin turning off their  
outputs immediately after the deselect command has been  
captured in the input registers. DCD RAMs hold the deselect  
command for one full cycle and then begin turning off their  
outputs just after the second rising edge of clock. The user may  
configure this SRAM for either mode of operation using the SCD  
mode input.  
Functional Description  
Applications  
The GS832218/36A-xxxV is a 37,748,736-bit high performance  
synchronous SRAM with a 2-bit burst address counter. Although  
of a type originally developed for Level 2 Cache applications  
supporting high performance CPUs, the device now finds  
application in synchronous SRAM applications, ranging from  
DSP main store to networking chip set support.  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write control  
inputs.  
Controls  
Addresses, data I/Os, chip enable (E1), address burst control  
FLXDrive™  
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,  
GW) are synchronous and are controlled by a positive-edge-  
triggered clock input (CK). Output enable (G) and power down  
control (ZZ) are asynchronous inputs. Burst cycles can be initiated  
with either ADSP or ADSC inputs. In Burst mode, subsequent  
burst addresses are generated internally and are controlled by  
ADV. The burst address counter may be configured to count in  
either linear or interleave order with the Linear Burst Order (LBO)  
input. The Burst function need not be used. New addresses can be  
loaded on every cycle with no degradation of chip performance.  
The ZQ pin allows selection between high drive strength (ZQ low)  
for multi-drop bus applications and normal drive strength (ZQ  
floating or high) point-to-point applications. See the Output Driver  
Characteristics chart for details.  
Core and Interface Voltages  
The GS832218/36A-xxxV operates on a 1.8 V or 2.5 V power  
supply. All inputs are 1.8 V or 2.5 V compatible. Separate output  
power (VDDQ) pins are used to decouple output noise from the  
internal circuits and are 1.8 V or 2.5 V compatible.  
Parameter Synopsis  
-333  
-250  
-200  
-150  
Unit  
t
3.0  
3.0  
3.0  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
KQ  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18)  
Curr (x36)  
365  
425  
290  
345  
250  
290  
215  
240  
mA  
mA  
t
5.0  
5.0  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
KQ  
Flow  
Through  
2-1-1-1  
tCycle  
Curr (x18)  
Curr (x36)  
270  
315  
245  
280  
210  
250  
200  
230  
mA  
mA  
Rev: 1.03 8/2013  
1/36  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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GS832236AB-150V GSI

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 		Cache SRAM, 1MX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS832236AB-150VT GSI

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 		Cache SRAM, 1MX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS832236AB-200 GSI

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GS832236AB-200I GSI

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GS832236AB-200IV GSI

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 		119 BGA
GS832236AB-200IVT GSI

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 		Cache SRAM, 1MX36, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS832236AB-200V GSI

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 		119 BGA
GS832236AB-250 GSI

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 		Cache SRAM, 1MX36, 5.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS832236AB-250I GSI

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 		Cache SRAM, 1MX36, 5.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS832236AB-250IT GSI

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 		Cache SRAM, 1MX36, 5.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119

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