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GS8320E18GT-133IT PDF预览

GS8320E18GT-133IT

更新时间： 2024-11-23 21:04:39
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
25页 1704K
描述
Cache SRAM, 2MX18, 8.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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GS8320E18GT-133IT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.74
最长访问时间：8.5 ns其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm内存密度：37748736 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：100字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：2MX18封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：2 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：PURE MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS8320E18GT-133IT 数据手册

 浏览型号GS8320E18GT-133IT的Datasheet PDF文件第2页浏览型号GS8320E18GT-133IT的Datasheet PDF文件第3页浏览型号GS8320E18GT-133IT的Datasheet PDF文件第4页浏览型号GS8320E18GT-133IT的Datasheet PDF文件第5页浏览型号GS8320E18GT-133IT的Datasheet PDF文件第6页浏览型号GS8320E18GT-133IT的Datasheet PDF文件第7页 
GS8320E18/32/36T-250/225/200/166/150/133  
250 MHz–133 MHz  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
2M x 18, 1M x 32, 1M x 36  
36Mb Sync Burst SRAMs  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipeline  
operation  
• Dual Cycle Deselect (DCD) operation  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP package  
• Pb-Free 100-lead TQFP package available  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by  
the user via the FT mode pin (Pin 14). Holding the FT mode  
pin low places the RAM iFlow Through mode, causing  
output data to bypass the Data Output Register. Holding FT  
high places the RAM in Pipeline mode, activating the rising-  
edge-triggered Data Output Register.  
DCD Pipelined Reads  
The GS8320E/32/36T is a DCD (Dual Cycle Deselect)  
pipelined synchronous SRAM. SCD (Single Cycle Deselect)  
versions are also available. DCD SRAMs pipeline disable  
commans to the same degree as read commands. DCD RAMs  
hold the deselect command for one full cycle and then begin  
turning off their outputs just after the second rising edge of  
clock.  
Functional Description  
Applications  
The GS8320E18/32/36T is a 37,748,736-bit high performance  
synchronous SRAM with a 2-bit burst address counter.  
Although of a type originally developed for Level 2 Cache  
applications supporting high performance CPUs, the device  
now finds application in synchronous SRAM applications,  
ranging from DSP main store to networking chip set support.  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Controls  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Outpt enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
cycles can be initiated with either ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Core and Interface Voltages  
The GS8320E18/32/36T operates on a 2.5 V or 3.3 V power  
supply. All input are 3.3 V and 2.5 V compatible. Separate  
output power (V  
) pins are used to decouple output noise  
DDQ  
from the internal circuits and are 3.3 V and 2.5 V compatible.  
Parameter Synopsis  
-250 -225 -200 -166 -150 -133 Unit  
t
2.5 2.7 3.0 3.5 3.8 4.0 ns  
4.0 4.4 5.0 6.0 6.6 7.5 ns  
KQ  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18) 285 265 245 220 210 185 mA  
Curr (x32/x36) 350 320 295 260 240 215 mA  
t
6.5 7.0 7.5 8.0 8.5 8.5 ns  
6.5 7.0 7.5 8.0 8.5 8.5 ns  
KQ  
Flow  
Through  
2-1-1-1  
tCycle  
Curr (x18) 205 195 185 175 165 155 mA  
Curr (x32/x36) 235 225 210 200 190 175 mA  
Rev: 1.02a 12/2007  
1/25  
© 2001, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...25

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与GS8320E18GT-133IT相关器件

型号 品牌 获取价格 描述 数据表
GS8320E18GT-133IV GSI

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 		Cache SRAM, 2MX18, 8.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8320E18GT-133T GSI

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 		Cache SRAM, 2MX18, 8.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8320E18GT-133VT GSI

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 		Cache SRAM, 2MX18, 8.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8320E18GT-150 GSI

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 		2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS8320E18GT-150I GSI

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 		2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS8320E18GT-150IT GSI

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 		暂无描述
GS8320E18GT-150IV GSI

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 		Cache SRAM, 2MX18, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8320E18GT-150T GSI

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 		Cache SRAM, 2MX18, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8320E18GT-150VT GSI

获取价格

 		Cache SRAM, 2MX18, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8320E18GT-166 GSI

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 		2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

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