Datasheet > GS82582T19GE-375I

GS82582T19GE-375I

更新时间： 2025-07-18 14:57:11

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页数	文件大小	规格书
28页	474K
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165 BGA

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GS82582T19GE-375I 数据手册

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GS82582T19/37GE-450/400/375/333

288Mb SigmaDDR-II+^TM

Burst of 2 SRAM

450 MHz–333 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

1.8 V V

1.8 V or 1.5 V I/O

SRAMs. The GS82582T19/37GE SigmaDDR-II+ SRAMs are

just one element in a family of low power, low voltage HSTL

I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) inputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

Clocking and Addressing Schemes

The GS82582T19/37GE SigmaDDR-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• RoHS-compliant 165-bump BGA package

Each internal read and write operation in a SigmaDDR-II+ B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore, the address field of a

SigmaDDR-II+ B2 RAM is always one address pin less than

the advertised index depth (e.g., the 16M x 18 has an 8M

addressable index).

SigmaDDR™ Family Overview

The GS82582T19/37GE are built in compliance with the

SigmaDDR-II+ SRAM pinout standard for Common I/O

synchronous SRAMs. They are 301,989,888-bit (288Mb)

Parameter Synopsis

-450

2.2 ns

0.45 ns

-400

2.5 ns

0.45 ns

-375

-333

3.0 ns

0.45 ns

tKHKH

tKHQV

2.66 ns

0.45 ns

Rev: 1.04b 11/2017

1/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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