GS82582T20/38GE-550/500/450/400
550 MHz–400 MHz
288Mb SigmaDDR-II+TM
Burst of 2 SRAM
165-Bump BGA
Commercial Temp
Industrial Temp
1.8 V V
DD
1.8 V or 1.5 V I/O
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Features
• 2.5 Clock Latency
TM
• Simultaneous Read and Write SigmaDDR Interface
• JEDEC-standard pinout and package
• Double Data Rate interface
Clocking and Addressing Schemes
The GS82582T20/38GE SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
Each internal read and write operation in a SigmaDDR-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore, the address field of a
SigmaDDR-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 16M x 18 has an 8M
addressable index).
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• RoHS-compliant 165-bump BGA package
SigmaDDR-II™ Family Overview
The GS82582T20/38GE are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 301,989,888-bit (288Mb)
SRAMs. The GS82582T20/38GE SigmaDDR-II+ SRAMs are
Parameter Synopsis
-550
-500
2.0 ns
0.45 ns
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
tKHKH
tKHQV
1.81 ns
0.45 ns
Rev: 1.04b 11/2017
1/27
© 2012, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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