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GS816273C-250IT PDF预览

GS816273C-250IT

更新时间： 2024-11-19 06:20:59
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
25页 1018K
描述
Cache SRAM, 256KX72, 2.6ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209

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GS816273C-250IT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 1 MM PITCH, BGA-209
针数：209Reach Compliance Code：unknown
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.48最长访问时间：2.6 ns
其他特性：PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLYJESD-30 代码：R-PBGA-B209
长度：22 mm内存密度：18874368 bit
内存集成电路类型：CACHE SRAM内存宽度：72
湿度敏感等级：3功能数量：1
端子数量：209字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX72封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.7 mm最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm

GS816273C-250IT 数据手册

 浏览型号GS816273C-250IT的Datasheet PDF文件第2页浏览型号GS816273C-250IT的Datasheet PDF文件第3页浏览型号GS816273C-250IT的Datasheet PDF文件第4页浏览型号GS816273C-250IT的Datasheet PDF文件第5页浏览型号GS816273C-250IT的Datasheet PDF文件第6页浏览型号GS816273C-250IT的Datasheet PDF文件第7页 
GS816273C-250/225  
209-Pin BGA  
Commercial Temp  
Industrial Temp  
250 MHz–225 MHz  
256K x 72  
18Mb S/DCD Sync Burst SRAMs  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
SCD and DCD Pipelined Reads  
Features  
The GS816273C is a SCD (Single Cycle Deselect) and DCD  
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD  
SRAMs pipeline disable commands to the same degree as read  
commands. SCD SRAMs pipeline deselect commands one  
stage less than read commands. SCD RAMs begin turning off  
their outputs immediately after the deselect command has been  
captured in the input registers. DCD RAMs hold the deselect  
command for one full cycle and then begin turning off their  
outputs just after the second rising edge of clock. The user may  
configure this SRAM for either mode of operation using the  
SCD mode input.  
• Single/Dual Cycle Deselect selectable  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• ZQ mode pin for user-selectable high/low output drive  
• 2.5 or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 209-bump BGA package  
Byte Write and Global Write  
Functional Description  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Applications  
The GS816273C is an 18,874,368-bit high performance  
synchronous SRAM with a 2-bit burst address counter.  
Although of a type originally developed for Level 2 Cache  
applications supporting high performance CPUs, the device  
now finds application in synchronous SRAM applications,  
ranging from DSP main store to networking chip set support.  
FLXDrive™  
The ZQ pin allows selection between high drive strength (ZQ  
low) for multi-drop bus applications and normal drive strength  
(ZQ floating or high) point-to-point applications. See the  
Output Driver Characteristics chart for details.  
Controls  
Addresses, data I/Os, chip enable (E1), address burst control  
inputs (ADSP, ADSC, ADV), and write control inputs (Bx,  
BW, GW) are synchronous and are controlled by a positive-  
edge-triggered clock input (CK). Output enable (G) and power  
down control (ZZ) are asynchronous inputs. Burst cycles can  
be initiated with either ADSP or ADSC inputs. In Burst mode,  
subsequent burst addresses are generated internally and are  
controlled by ADV. The burst address counter may be  
configured to count in either linear or interleave order with the  
Linear Burst Order (LBO) input. The Burst function need not  
be used. New addresses can be loaded on every cycle with no  
degradation of chip performance.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Core and Interface Voltages  
The GS816273C operates on a 2.5 V or 3.3 V power supply.  
All input are 3.3 V and 2.5 V compatible. Separate output  
power (V  
) pins are used to decouple output noise from the  
DDQ  
internal circuits and are 3.3 V and 2.5 V compatible.  
Parameter Synopsis  
-250  
-225  
Unit  
Pipeline  
3-1-1-1  
t
2.6  
4.0  
2.6  
4.5  
ns  
ns  
KQ  
tCycle  
3.3 V  
2.5 V  
Curr (x72)  
Curr (x72)  
430  
410  
400  
375  
mA  
mA  
Rev: 1.03 7/2004  
1/25  
© 2002, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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