Datasheet > GS8161E18GD-133IT

GS8161E18GD-133IT

更新时间： 2024-11-26 09:10:27

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
36页	935K
描述
Cache SRAM, 1MX18, 8.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

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GS8161E18(T/D)/GS816132(D)/GS816136(T/D)

250 MHz–133 MHz

100-Pin TQFP & 165-Bump BGA

Commercial Temp

Industrial Temp

1M x 18, 512K x 32, 512K x 36

18Mb Sync Burst SRAMs

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

with the Linear Burst Order (LBO) input. The Burst function need not

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

• Dual Cycle Deselect (DCD) operation

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP and 165-bump BGA

packages

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the user

via the FT mode pin (Pin 14). Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the Data

Output Register. Holding FT high places the RAM in Pipeline mode,

activating the rising-edge-triggered Data Output Register.

DCD Pipelined Reads

The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) is a DCD

(Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single

Cycle Deselect) versions are also available. DCD SRAMs pipeline

disable commands to the same degree as read commands. DCD

RAMs hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of clock.

Functional Description

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable (BW)

input combined with one or more individual byte write signals (Bx).

In addition, Global Write (GW) is available for writing all bytes at one

time, regardless of the Byte Write control inputs.

Applications

The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) is a

18,874,368-bit high performance synchronous SRAM with a 2-bit

burst address counter. Although of a type originally developed for

Level 2 Cache applications supporting high performance CPUs, the

device now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of

the ZZ signal, or by stopping the clock (CK). Memory data is retained

during Sleep mode.

Controls

Addresses, data I/Os, chip enable (E1), address burst control inputs

(ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are

synchronous and are controlled by a positive-edge-triggered clock

input (CK). Output enable (G) and power down control (ZZ) are

asynchronous inputs. Burst cycles can be initiated with either ADSP

or ADSC inputs. In Burst mode, subsequent burst addresses are

generated internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or interleave order

Core and Interface Voltages

The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) operates on

a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V

compatible. Separate output power (V_DDQ) pins are used to decouple

output noise from the internal circuits and are 3.3 V and 2.5 V

compatible.

Parameter Synopsis

-250

-225

-200

-166 -150 -133 Unit

Pipeline

3-1-1-1

t_KQ

2.5

4.0

2.7

4.4

3.0

5.0

3.4

6.0

3.8

6.7

4.0

7.5

tCycle

Curr (x18)

Curr (x36)

280

330

255

300

230

270

200

230

185

215

165

190

3.3 V

2.5 V

Curr (x18)

Curr (x36)

275

320

250

295

230

265

195

225

180

210

165

185

Flow Through

2-1-1-1

t_KQ

5.5

6.0

6.5

7.0

7.5

8.5

tCycle

Curr (x18)

Curr (x36)

175

200

165

190

160

180

150

170

145

165

135

150

3.3 V

2.5 V

Curr (x18)

Curr (x36)

175

200

165

190

160

180

150

170

145

165

135

150

Rev: 2.14 3/2005

1/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...36

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与GS8161E18GD-133IT相关器件

型号	品牌	获取价格	描述	数据表
GS8161E18GD-133T	GSI	获取价格	Cache SRAM, 1MX18, 8.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161E18GD-150	GSI	获取价格	Cache SRAM, 1MX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161E18GD-150I	GSI	获取价格	Cache SRAM, 1MX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161E18GD-166T	GSI	获取价格	Cache SRAM, 1MX18, 7ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161E18GD-200I	GSI	获取价格	Cache SRAM, 1MX18, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161E18GD-200IT	GSI	获取价格	Cache SRAM, 1MX18, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161E18GD-225I	GSI	获取价格	Cache SRAM, 1MX18, 6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161E18GD-225IT	GSI	获取价格	Cache SRAM, 1MX18, 6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161E18GD-225T	GSI	获取价格	Cache SRAM, 1MX18, 6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161E18GD-250	GSI	获取价格	Cache SRAM, 1MX18, 5.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

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