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GS8161E18D-200T PDF预览

GS8161E18D-200T

更新时间： 2024-11-18 15:44:07
品牌 Logo 应用领域
GSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
36页 935K
描述
Cache SRAM, 1MX18, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

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GS8161E18D-200T 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：BGA, BGA165,11X15,40
针数：165Reach Compliance Code：unknown
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.72最长访问时间：6.5 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：15 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：165
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：1MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3 V认证状态：Not Qualified
最大待机电流：0.02 A最小待机电流：2.3 V
子类别：SRAMs最大压摆率：0.215 mA
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

GS8161E18D-200T 数据手册

 浏览型号GS8161E18D-200T的Datasheet PDF文件第2页浏览型号GS8161E18D-200T的Datasheet PDF文件第3页浏览型号GS8161E18D-200T的Datasheet PDF文件第4页浏览型号GS8161E18D-200T的Datasheet PDF文件第5页浏览型号GS8161E18D-200T的Datasheet PDF文件第6页浏览型号GS8161E18D-200T的Datasheet PDF文件第7页 
GS8161E18(T/D)/GS816132(D)/GS816136(T/D)  
250 MHz–133 MHz  
100-Pin TQFP & 165-Bump BGA  
Commercial Temp  
Industrial Temp  
1M x 18, 512K x 32, 512K x 36  
18Mb Sync Burst SRAMs  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
with the Linear Burst Order (LBO) input. The Burst function need not  
be used. New addresses can be loaded on every cycle with no  
degradation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipeline  
operation  
• Dual Cycle Deselect (DCD) operation  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP and 165-bump BGA  
packages  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by the user  
via the FT mode pin (Pin 14). Holding the FT mode pin low places the  
RAM in Flow Through mode, causing output data to bypass the Data  
Output Register. Holding FT high places the RAM in Pipeline mode,  
activating the rising-edge-triggered Data Output Register.  
DCD Pipelined Reads  
The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) is a DCD  
(Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single  
Cycle Deselect) versions are also available. DCD SRAMs pipeline  
disable commands to the same degree as read commands. DCD  
RAMs hold the deselect command for one full cycle and then begin  
turning off their outputs just after the second rising edge of clock.  
Functional Description  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable (BW)  
input combined with one or more individual byte write signals (Bx).  
In addition, Global Write (GW) is available for writing all bytes at one  
time, regardless of the Byte Write control inputs.  
Applications  
The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) is a  
18,874,368-bit high performance synchronous SRAM with a 2-bit  
burst address counter. Although of a type originally developed for  
Level 2 Cache applications supporting high performance CPUs, the  
device now finds application in synchronous SRAM applications,  
ranging from DSP main store to networking chip set support.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion (High) of  
the ZZ signal, or by stopping the clock (CK). Memory data is retained  
during Sleep mode.  
Controls  
Addresses, data I/Os, chip enable (E1), address burst control inputs  
(ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are  
synchronous and are controlled by a positive-edge-triggered clock  
input (CK). Output enable (G) and power down control (ZZ) are  
asynchronous inputs. Burst cycles can be initiated with either ADSP  
or ADSC inputs. In Burst mode, subsequent burst addresses are  
generated internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or interleave order  
Core and Interface Voltages  
The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) operates on  
a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V  
compatible. Separate output power (VDDQ) pins are used to decouple  
output noise from the internal circuits and are 3.3 V and 2.5 V  
compatible.  
Parameter Synopsis  
-250  
-225  
-200  
-166 -150 -133 Unit  
Pipeline  
3-1-1-1  
tKQ  
2.5  
4.0  
2.7  
4.4  
3.0  
5.0  
3.4  
6.0  
3.8  
6.7  
4.0  
7.5  
ns  
ns  
tCycle  
Curr (x18)  
Curr (x36)  
280  
330  
255  
300  
230  
270  
200  
230  
185  
215  
165  
190  
mA  
mA  
3.3 V  
2.5 V  
Curr (x18)  
Curr (x36)  
275  
320  
250  
295  
230  
265  
195  
225  
180  
210  
165  
185  
mA  
mA  
Flow Through  
2-1-1-1  
tKQ  
5.5  
5.5  
6.0  
6.0  
6.5  
6.5  
7.0  
7.0  
7.5  
7.5  
8.5  
8.5  
ns  
ns  
tCycle  
Curr (x18)  
Curr (x36)  
175  
200  
165  
190  
160  
180  
150  
170  
145  
165  
135  
150  
mA  
mA  
3.3 V  
2.5 V  
Curr (x18)  
Curr (x36)  
175  
200  
165  
190  
160  
180  
150  
170  
145  
165  
135  
150  
mA  
mA  
Rev: 2.14 3/2005  
1/36  
© 1999, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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