Datasheet > GS8160F36DGT-7.5

GS8160F36DGT-7.5

更新时间： 2023-12-06 20:02:09

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
22页	292K
描述
100 TQFP

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数据手册

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GS8160F36DGT-7.5 数据手册

GS8160F18/32/36DGT-6.5/7.5

TQFP Pin Description

Symbol

A0, A1

Type

Description

Address field LSBs and Address Counter preset Inputs

Address Inputs

DQ^A

DQB

DQC

DQD

I/O

Data Input and Output pins

BA, BB

BC, BD

Byte Write—Writes all enabled bytes; active low

Byte Write Enable for DQA, DQB Data I/Os; active low

Byte Write Enable for DQC, DQD Data I/Os; active low

Clock Input Signal; active high

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

E1, E3

E²

Chip Enable; active high

Output Enable; active low

ADV

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

ADSP, ADSC

LBO

Linear Burst Order mode; active low

Core power supply

I/O and Core Ground

Output driver power supply

No Connect

DDQ

Rev: 1.01 10/2013

5/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

1 2 3 456 7 8...22

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