Datasheet > GS81302T18E-333

GS81302T18E-333

更新时间： 2022-12-29 21:21:46

品牌	Logo	应用领域
GSI		双倍数据速率静态存储器
页数	文件大小	规格书
36页	483K
描述
144Mb SigmaDDRTM-II Burst of 2 SRAM

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数据手册

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GS81302T18E-333 数据手册

GS81302T08/09/18/36E-375/350/333/300/250

Pin Description Table

Symbol

Description

Type

Comments

Synchronous Address Inputs

Input

—

Read: Active High

Write: Active Low

R/W

Synchronous Read/Write

Synchronous Byte Writes

Nybble Write Control Pin

Input

Active Low

x18/x36 only

BW0–BW3

NW0–NW1

Active Low

x8 only

Synchronous Load Pin

Input Clock

Input

Active Low

Active High

Input Clock

Input

Active Low

Output Clock

Input

Active High

Output Clock

Input

Active Low

TMS

TDI

TCK

TDO

V_REF

Test Mode Select

Test Data Input

Input

—

Input

—

Test Clock Input

Input

—

Test Data Output

HSTL Input Reference Voltage

Output Impedance Matching Input

Must Connect Low

Data I/O

Output

Input

—

MCL

Input

—

Input/Output

Input

Three State

Active Low

—

Disable DLL when low

Output Echo Clock

Power Supply

Doff

Output

Supply

—

V_DD

1.8 V Nominal

V_DDQ

V_SS

Isolated Output Buffer Supply

Power Supply: Ground

No Connect

Supply

—

1.8 V or 1.5 V Nominal

—

Notes:

1. NC = Not Connected to die or any other pin

2. C, C, K, K cannot be set to V voltage.

REF

3. When ZQ pin is directly connected to V , output impedance is set to minimum and it cannot be connected to ground or left unconnected.

DDQ

Rev: 1.03b 12/2011

6/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

1...3 4 567 8 9...36

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