Datasheet > GS81302S18E-250T

GS81302S18E-250T

更新时间： 2024-02-21 22:04:29

品牌	Logo	应用领域
GSI		双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
35页	1322K
描述
DDR SRAM, 8MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-165

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GS81302S18E-250T 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Not Recommended	零件包装代码：	BGA
包装说明：	LBGA,	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.05
Is Samacsys：	N	最长访问时间：	0.45 ns
其他特性：	PIPELINED ARCHITECTURE	JESD-30 代码：	R-PBGA-B165
长度：	17 mm	内存密度：	150994944 bit
内存集成电路类型：	DDR SRAM	内存宽度：	18
功能数量：	1	端子数量：	165
字数：	8388608 words	字数代码：	8000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	8MX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	1.5 mm
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	15 mm	Base Number Matches：	1

GS81302S18E-250T 数据手册

浏览型号GS81302S18E-250T的Datasheet PDF文件第10页

GS81302S08/09/18/36E-375/350/333/300/250

Background

Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the

other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are

needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a

separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control

protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at

the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write

addresses like SigmaCIO SRAMs, but in a separate I/O configuration.

Like a SigmaQuad SRAM, a SigmaSIO DDR-II SRAM can execute an alternating sequence of reads and writes. However, doing

so results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would

keep both ports running at capacity full time. On the other hand, the SigmaSIO device can accept a continuous stream of read

commands and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts

the user from loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice

the random address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device.

SigmaDDR (CIO) SRAMs offer this same advantage, but do not have the separate Data In and Data Out pins offered on the

SigmaSIO SRAMs. Therefore, SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of

burst traffic between two electrically independent busses is desired.

Each of the three SigmaQuad Family SRAMs—SigmaQuad, SigmaDDR, and SigmaSIO—supports similar address rates because

random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are

based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how

the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and

disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to

the application at hand.

Burst of 2 SigmaSIO DDR-II SRAM DDR Read

The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on

the R/W pin begins a read cycle. The two resulting data output transfers begin after the next rising edge of the K clock. Data is

clocked out by the next rising edge of the C if it is active. Otherwise, data is clocked out at the next rising edge of K. The next data

chunk is clocked out on the rising edge of C, if active. Otherwise, data is clocked out on the rising edge of K.

Burst of 2 SigmaSIO DDR-II SRAM DDR Write

The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the

R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K.

Rev: 1.03b 12/2011

7/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

1...4 5 678 9 10...35

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型号	品牌	描述	获取价格	数据表
GS81302S18E-300	GSI	165 BGA	获取价格
GS81302S18E-300I	GSI	165 BGA	获取价格
GS81302S18E-333	GSI	165 BGA	获取价格
GS81302S18E-333I	GSI	165 BGA	获取价格
GS81302S18E-350	GSI	165 BGA	获取价格
GS81302S18E-350I	GSI	165 BGA	获取价格

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