Datasheet > GS81302R37GE-400I

GS81302R37GE-400I

更新时间： 2023-01-03 06:03:36

品牌	Logo	应用领域
GSI		双倍数据速率静态存储器
页数	文件大小	规格书
31页	1087K
描述
DDR SRAM, 4MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-165

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Preliminary

GS81302R19/37E-400/375

400 MHz–375 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

144Mb SigmaCIO DDR-II+

Burst of 4 SRAM

1.8 V V

1.8 V and 1.5 V I/O

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaCIO™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36 and x18) and Nybble Write (x8) function

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaCIO™ Family Overview

The GS81302R19/37E are built in compliance with the

SigmaCIO DDR-II+ SRAM pinout standard for Common I/O

synchronous SRAMs. They are 150,994,944-bit (144Mb)

SRAMs. The GS81302R19/37E SigmaCIO SRAMs are just

one element in a family of low power, low voltage HSTL I/O

SRAMs designed to operate at the speeds needed to implement

economical high performance networking systems.

Clocking and Addressing Schemes

The GS81302R19/37E SigmaCIO DDR-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Common I/O SigmaCIO DDR-II+ B4 RAMs always transfer

data in four packets. When a new address is loaded, A0 and A1

preset an internal 2 bit linear address counter. The counter

increments by 1 for each beat of a burst of four data transfer.

The counter always wraps to 00 after reaching 11, no matter

where it starts.

Rev: 1.00 10/2007

1/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...31

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与GS81302R37GE-400I相关器件

型号	品牌	获取价格	描述	数据表
GS81302R37GE-400IT	GSI	获取价格	DDR SRAM, 4MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-165
GS81302S08	GSI	获取价格	144Mb SigmaSIOTM DDR -II Burst of 2 SRAM
GS81302S08E-167IT	GSI	获取价格	DDR SRAM, 8MX8, 0.5ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165
GS81302S08E-200I	GSI	获取价格	DDR SRAM, 8MX8, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165
GS81302S08E-200IT	GSI	获取价格	DDR SRAM, 8MX8, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165
GS81302S08E-250	GSI	获取价格	165 BGA
GS81302S08E-250I	GSI	获取价格	165 BGA
GS81302S08E-250IT	GSI	获取价格	DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-165
GS81302S08E-250T	GSI	获取价格	DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-165
GS81302S08E-300	GSI	获取价格	165 BGA

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