Datasheet > GS81302QT38AGD-450I

GS81302QT38AGD-450I

更新时间： 2023-11-02 19:29:11

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
25页	426K
描述
165 BGA

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Preliminary

GS81302QT20/38AGD-500/450/400

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are

needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O

SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from

Separate I/O SRAMs can cut the RAM’s bandwidth in half.

SigmaQuad-II B2 SRAM DDR Read

The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R,

begins a read cycle. Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.

SigmaQuad-II B2 SRAM DDR Write

The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of

K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is

clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on

the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle.

Special Functions

Byte Write Control

Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with

a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be

stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low

during the data in sample times in a write sequence.

Each write enable command and write address loaded into the RAM provides the base address for a 2beat data transfer. The x18

version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any

write sequence.

Example x18 RAM Write Sequence using Byte Write Enables

Data In Sample Time

BW0

BW1

D0–D8

Data In

D9–D17

Don’t Care

Data In

Beat 1

Beat 2

Don’t Care

Resulting Write Operation

Byte 1

D0–D8

Byte 2

D9–D17

Byte 3

D0–D8

Byte 4

D9–D17

Written

Unchanged

Written

Beat 1

Beat 2

FLXDrive-II Output Driver Impedance Control

HSTL I/O SigmaQuad-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to

V_SSvia an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be

5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is

Rev: 1.00a 5/2017

5/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

1 2 3 456 7 8...25

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与GS81302QT38AGD-450I相关器件

型号	品牌	获取价格	描述	数据表
GS81302QT38AGD-500	GSI	获取价格	144Mb SigmaQuad-IITM Burst of 2 SRAM
GS81302QT38AGD-500I	GSI	获取价格	144Mb SigmaQuad-IITM Burst of 2 SRAM
GS81302R08	GSI	获取价格	144Mb SigmaDDRTM-II Burst of 4 SRAM
GS81302R08E-200	GSI	获取价格	DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, BGA-165
GS81302R08E-200T	GSI	获取价格	DDR SRAM, 4MX8, 0.45ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, BGA-165
GS81302R08E-250	GSI	获取价格	165 BGA
GS81302R08E-250I	GSI	获取价格	165 BGA
GS81302R08E-300	GSI	获取价格	165 BGA
GS81302R08E-300I	GSI	获取价格	165 BGA
GS81302R08E-333	GSI	获取价格	165 BGA

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