Preliminary
GS81302QT20/38AGD-500/450/400
Pin Description Table
Symbol
Description
Synchronous Address Inputs
Synchronous Read
Synchronous Write
Synchronous Byte Writes
Input Clock
Type
Input
Comments
SA
R
—
Input
Active Low
W
Input
Active Low
BW0–BW3
K
Input
Active Low
Input
Active High
K
Input Clock
Input
Active Low
TMS
TDI
Test Mode Select
Input
—
Test Data Input
Input
—
TCK
TDO
VREF
Test Clock Input
Input
—
Test Data Output
Output
Input
—
HSTL Input Reference Voltage
Output Impedance Matching Input
Synchronous Data Outputs
Synchronous Data Inputs
Disable PLL when low
Output Echo Clock
—
ZQ
Qn
Input
—
Output
Input
—
Dn
—
Active Low
—
Input
Doff
CQ
CQ
VDD
Output
Output
Supply
Output Echo Clock
—
Power Supply
1.8 V Nominal
VDDQ
VSS
Isolated Output Buffer Supply
Power Supply: Ground
Q Valid Output
Supply
Supply
Output
1.8 V or 1.5 V Nominal
—
—
QVLD
Low = Low Impedance Range
High/Float = High Impedance Range
ODT
On-Die Termination
No Connect
Input
—
NC
—
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to V , output impedance is set to minimum value and it cannot be connected to ground or left
DDQ
unconnected.
3. K and K cannot be set to V
voltage.
REF
Rev: 1.00a 5/2017
4/25
© 2017, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.