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GS81302D10E-300 PDF预览

GS81302D10E-300

更新时间: 2024-12-02 00:46:43
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页数 文件大小 规格书
31页 517K
描述
JEDEC-standard pinout and package

GS81302D10E-300 数据手册

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GS81302D07/10/19/37E-450/400/350/333/300  
450 MHz–300 MHz  
144Mb SigmaQuad-II+TM  
Burst of 4 SRAM  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
1.8 V V  
DD  
1.8 V and 1.5 V I/O  
are just one element in a family of low power, low voltage  
HSTL I/O SRAMs designed to operate at the speeds needed to  
implement economical high performance networking systems.  
Features  
• 2.0 clock Latency  
• Simultaneous Read and Write SigmaQuad™ Interface  
• JEDEC-standard pinout and package  
• Dual Double Data Rate interface  
• Byte Write controls sampled at data-in time  
• Burst of 4 Read and Write  
• On-Die Termination (ODT) on Data (D), Byte Write (BW),  
and Clock (K, K) inputs  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
Clocking and Addressing Schemes  
The GS81302D07/10/19/37E SigmaQuad-II+ SRAMs are  
synchronous devices. They employ two input register clock  
inputs, K and K. K and K are independent single-ended clock  
inputs, not differential inputs to a single differential clock input  
buffer.  
• Pipelined read operation  
• Fully coherent read and write pipelines  
• ZQ pin for programmable output drive strength  
• Data Valid Pin (QVLD) Support  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
Each internal read and write operation in a SigmaQuad-II+ B4  
RAM is four times wider than the device I/O bus. An input  
data bus de-multiplexer is used to accumulate incoming data  
before it is simultaneously written to the memory array. An  
output data multiplexer is used to capture the data produced  
from a single memory array read and then route it to the  
appropriate output drivers as needed. Therefore the address  
field of a SigmaQuad-II+ B4 RAM is always two address pins  
less than the advertised index depth (e.g., the 16M x 8 has a  
4M addressable index).  
SigmaQuadFamily Overview  
The GS81302D07/10/19/37E are built in compliance with the  
SigmaQuad-II+ SRAM pinout standard for Separate I/O  
synchronous SRAMs. They are 150,994,944-bit (144Mb)  
SRAMs. The GS81302D07/10/19/37E SigmaQuad SRAMs  
Parameter Synopsis  
-450  
2.2 ns  
0.45 ns  
-400  
2.5 ns  
0.45 ns  
-350  
2.86 ns  
0.45 ns  
-333  
-300  
3.3 ns  
0.45 ns  
tKHKH  
tKHQV  
3.0 ns  
0.45 ns  
Rev: 1.04 4/2011  
1/31  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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