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GS81284Z18GB-200V PDF预览

GS81284Z18GB-200V

更新时间: 2024-10-02 19:42:11
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
28页 629K
描述
ZBT SRAM, 8MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-119

GS81284Z18GB-200V 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:BGA,针数:119
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41Factory Lead Time:10 weeks
风险等级:1.73最长访问时间:7.5 ns
其他特性:PIPELINE AND FLOW THROUGH ARCHITECTURE, IT ALSO OPERATES WITH 2.3V TO 2.7V SUPPLYJESD-30 代码:R-PBGA-B119
JESD-609代码:e1长度:22 mm
内存密度:150994944 bit内存集成电路类型:ZBT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:119
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX18
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.99 mm
最大供电电压 (Vsup):2 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

GS81284Z18GB-200V 数据手册

 浏览型号GS81284Z18GB-200V的Datasheet PDF文件第2页浏览型号GS81284Z18GB-200V的Datasheet PDF文件第3页浏览型号GS81284Z18GB-200V的Datasheet PDF文件第4页浏览型号GS81284Z18GB-200V的Datasheet PDF文件第5页浏览型号GS81284Z18GB-200V的Datasheet PDF文件第6页浏览型号GS81284Z18GB-200V的Datasheet PDF文件第7页 
GS81284Z18/36B-xxxV  
119-Bump BGA  
Commercial Temp  
Industrial Temp  
200 MHz167 MHz  
144Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
Because it is a synchronous device, address, data inputs, and  
read/write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
Features  
• NBT (No Bus Turn Around) functionality allows zero wait  
Read-Write-Read bus utilization; fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 1.8 V 2.5 V core power supply  
• 1.8 V or 2.5 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• ZQ mode pin for user-selectable high/low output drive  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• LBO pin for Linear or Interleave Burst mode  
• Pin-compatible with 8Mb, 36Mb, and 72Mb devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
• JEDEC-standard 119-BGA package  
The GS81284Z18/36-xxxV may be configured by the user to  
operate in Pipeline or Flow Through mode. Operating as a  
pipelined synchronous device, in addition to the rising-edge-  
triggered registers that capture input signals, the device  
incorporates a rising edge triggered output register. For read  
cycles, pipelined SRAM output data is temporarily stored by  
the edge-triggered output register during the access cycle and  
then released to the output drivers at the next rising edge of  
clock.  
• RoHS-compliant 119-BGA packages available  
Functional Description  
The GS81284Z18/36(B)-xxxV is a 144Mbit Synchronous  
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL  
or other pipelined read/double late write or flow through read/  
single late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS81284Z18/36-xxxV is implemented with GSI's high  
performance CMOS technology and is available in a JEDEC-  
standard 119-bump p BGA package.  
Parameter Synopsis  
-200  
-167  
Unit  
tKQ  
3.0  
5.0  
3.4  
6.0  
ns  
ns  
tCycle  
Pipeline  
3-1-1-1  
Curr (x18)  
Curr (x36)  
420  
480  
385  
430  
mA  
mA  
tKQ  
7.5  
7.5  
8.0  
8.0  
ns  
ns  
tCycle  
Flow Through  
2-1-1-1  
Curr (x18)  
Curr (x36)  
340  
370  
330  
360  
mA  
mA  
Rev: 1.02 7/2010  
1/28  
© 2007, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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