Datasheet > GS8128236GD-250IVT

GS8128236GD-250IVT

更新时间： 2024-11-24 15:43:15

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
34页	600K
描述
Cache SRAM, 4MX36, CMOS, PBGA165, BGA-165

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GS8128236GD-250IVT 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	LBGA,	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.B	HTS代码：	8542.32.00.41
风险等级：	5.67	其他特性：	IT ALSO OPERATES AT 2.3 TO 2.7 V SUPPLY VOLTAGE
JESD-30 代码：	R-PBGA-B165	长度：	15 mm
内存密度：	150994944 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	36	功能数量：	1
端子数量：	165	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
组织：	4MX36	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	1.4 mm
最大供电电压 (Vsup)：	2 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	13 mm
Base Number Matches：	1

GS8128236GD-250IVT 数据手册

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Preliminary

GS8128218/36(GB/GD)-xxxV

119- & 165-Bump BGA

Commercial Temp

Industrial Temp

333 MHz–200 MHz

8M x 18, 4M x 36

144Mb S/DCD Sync Burst SRAMs

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Flow Through/Pipeline Reads

Features

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 1.8 V +10%/–10% core power supply

• 2.5 V +10%/–10% core power supply

• 1.8 V or 2.5 V I/O supply

SCD and DCD Pipelined Reads

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

The GS8128218/36 is a SCD (Single Cycle Deselect) and DCD

(Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

• ZZ pin for automatic power-down

• RoHS-compliant 119-bump and 165-bump BGA packages

Functional Description

Applications

The GS8128218/36 is a 150,994,944-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

FLXDrive™

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Core and Interface Voltages

The GS8128218/36 operates on a 1.8 V or 2.5 V power supply.

All input are 1.8 V or 2.5 V compatible. Separate output power

(V_DDQ) pins are used to decouple output noise from the internal

circuits and are 1.8 V or 2.5 V compatible.

Parameter Synopsis

-333

2.5

3.0

-250

-200

Unit

t_KQ

tCycle

2.5

4.0

3.0

5.0

Pipeline

3-1-1-1

Curr (x18)

Curr (x36)

565

660

445

520

380

440

t_KQ

tCycle

4.5

5.5

6.5

Flow Through

2-1-1-1

Curr (x18)

Curr (x36)

415

485

350

390

305

355

Rev: 1.00 9/2015

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...34

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与GS8128236GD-250IVT相关器件

型号	品牌	获取价格	描述	数据表
GS8128236GD-250V	GSI	获取价格	Cache SRAM, 4MX36, CMOS, PBGA165, BGA-165
GS8128236GD-333	GSI	获取价格	8M x 18, 4M x 36 144Mb S/DCD Sync Burst SRAMs
GS8128236GD-333I	GSI	获取价格	165 BGA
GS8128236GD-333IV	GSI	获取价格	8M x 18, 4M x 36 144Mb S/DCD Sync Burst SRAMs
GS8128236GD-333IVT	GSI	获取价格	Cache SRAM, 4MX36, CMOS, PBGA165, BGA-165
GS8128236GD-333V	GSI	获取价格	Cache SRAM, 4MX36, CMOS, PBGA165, BGA-165
GS8128236GD-333VT	GSI	获取价格	Cache SRAM, 4MX36, CMOS, PBGA165, BGA-165
GS8128236GD-400	GSI	获取价格	8M x 18, 4M x 36 144Mb S/DCD Sync Burst SRAMs
GS8128236GD-400I	GSI	获取价格	165 BGA
GS81282Z18GB-200	GSI	获取价格	144Mb Pipelined and Flow Through Synchronous NBT SRAM

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