GS71116TP/J/U
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
10, 12, 15ns
3.3V VDD
Center VDD & VSS
64K x 16
1Mb Asynchronous SRAM
SOJ 64K x 16 Pin Configuration
Features
• Fast access time: 10, 12, 15ns
A4
1
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
• CMOS low power operation: 100/85/70 mA at min. cycle time.
• Single 3.3V ± 0.3V power supply
• All inputs and outputs are TTL compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: -40° to 85°C
• Package line up
A3
A6
2
A2
A7
3
A1
OE
4
Top view
A0
UB
5
CE
LB
6
DQ1
DQ2
DQ3
DQ4
VDD
DQ16
DQ15
DQ14
7
8
9
J: 400mil, 44 pin SOJ package
TP: 400mil, 44 pin TSOP Type II package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
10
11
12
13
14
15
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
44 pin
SOJ
VSS
DQ5
DQ6
DQ7
DQ8
WE
Description
The GS71116 is a high speed CMOS static RAM organized as
65,536-words by 16-bits. Static design eliminates the need for exter-
nal clocks or timing strobes. Operating on a single 3.3V power supply
and all inputs and outputs are TTL compatible. The GS71116 is avail-
able in a 6x8 mm Fine Pitch BGA package as well as in 400 mil SOJ
and 400 mil TSOP Type-II packages.
16
17
18
A15
A14
A13
A12
NC
A8
A9
19
20
21
22
A10
A11
NC
Pin Descriptions
Fine Pitch BGA 64K x 16 Bump Configuration
Symbol
A0 to A15
Description
Address input
1
2
3
4
5
6
DQ1 to DQ16
CE
Data input/output
Chip enable input
A
B
C
D
E
F
LB
OE
A0
A3
A1
A4
A6
A7
A2
NC
Lower byte enable input
(DQ1 to DQ8)
LB
DQ16 UB
CE
DQ1
Upper byte enable input
(DQ9 to DQ16)
DQ14 DQ15 A5
VSS DQ13 NC
VDD DQ12 NC
DQ11 DQ10 A8
DQ2 DQ3
DQ4 VDD
UB
WE
OE
VDD
VSS
NC
Write enable input
Output enable input
+3.3V power supply
Ground
NC DQ5 VSS
A9
DQ7 DQ6
WE DQ8
G
H
DQ9 NC
NC A12
A10
A13
A11
A14
No connect
A15
NC
6mm x 8mm, 0.75mm Bump Pitch
Top View
Rev: 1.06 6/2000
1/15
© 1999, Giga Semiconductor, Inc.
M
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.