Datasheet > GS256418GB-250IV

GS256418GB-250IV

更新时间： 2024-01-01 19:42:42

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
33页	422K
描述
16M x 18, 8M x 36 288Mb DCD Sync Burst SRAMs

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技术参数
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GS256418GB-250IV 技术参数

生命周期：	Active	包装说明：	BGA,
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.79
其他特性：	IT ALSO OPERATES AT 2.3 V TO 2.7 V SUPPLY VOLTAGE	JESD-30 代码：	R-PBGA-B119
长度：	22 mm	内存密度：	301989888 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
功能数量：	1	端子数量：	119
字数：	16777216 words	字数代码：	16000000
工作模式：	SYNCHRONOUS	组织：	16MX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	座面最大高度：	1.99 mm
最大供电电压 (Vsup)：	2 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
宽度：	14 mm	Base Number Matches：	1

GS256418GB-250IV 数据手册

GS8256418/36(GB/GD)-xxxV

119- & 165-Bump BGA

Commercial Temp

Industrial Temp

333 MHz–200 MHz

16M x 18, 8M x 36

288Mb DCD Sync Burst SRAMs

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 1.8 V +10%/–10% core power supply

• 2.5 V +10%/–10% core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• ZZ pin for automatic power-down

• RoHS-compliant 119-bump and 165-bump BGA packages

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

DCD Pipelined Reads

The GS8256418/36-xxxV is a DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. DCD SRAMs pipeline disable

commands to the same degree as read commands. DCD RAMs

hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of clock.

Functional Description

Applications

The GS8256418/36-xxxV is a 301,989,888-bit high performance

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Controls

FLXDrive™

Addresses, data I/Os, chip enable (E1), address burst control

The ZQ pin allows selection between high drive strength (ZQ low)

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Core and Interface Voltages

The GS8256418/36-xxxV operates on a 1.8 V or 2.5 V power

supply. All input are 31.8 V or 2.5 V compatible. Separate output

Parameter Synopsis

-333

2.5

3.0

-250

-200

Unit

t_KQ

2.5

4.0

3.0

5.0

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x36)

630

690

520

570

450

490

t_KQ

tCycle

4.5

5.5

6.5

Flow Through

2-1-1-1

Curr (x18)

Curr (x36)

490

530

430

470

400

440

Rev: 1.03 5/2017

1/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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与GS256418GB-250IV相关器件

型号	品牌	获取价格	描述	数据表
GS256418GB-250IVT	GSI	获取价格	Cache SRAM, 16MX18, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-119
GS25A	MEANWELL	获取价格	20~25WAC-DC Single Output Desktop
GS25A	YANGJIE	获取价格	SMB
GS25A_11	MEANWELL	获取价格	20~25WAC-DC Single Output Desktop
GS25A_12	MEANWELL	获取价格	20~25WAC-DC Single Output Desktop
GS25A05	MEANWELL	获取价格	20~25WAC-DC Single Output Desktop
GS25A05-P1J	MEANWELL	获取价格	20~25WAC-DC Single Output Desktop
GS25A07	MEANWELL	获取价格	20~25WAC-DC Single Output Desktop
GS25A07-P1J	MEANWELL	获取价格	20~25WAC-DC Single Output Desktop
GS25A09	MEANWELL	获取价格	20~25WAC-DC Single Output Desktop

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