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GP2015/1G/FP2Q

更新时间： 2024-01-29 15:06:15
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信电信集成电路
页数 文件大小 规格书
24页 212K
描述
Telecom Circuit, 1-Func, CMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BBC, LQFP-48

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GP2015/1G/FP2Q 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：LFQFP, QFP48,.35SQ,20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.84
JESD-30 代码：S-PQFP-G48JESD-609代码：e3
长度：7 mm湿度敏感等级：3
功能数量：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP48,.35SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
座面最大高度：1.6 mm子类别：Other Telecom ICs
最大压摆率：0.077 mA标称供电电压：3 V
表面贴装：YES技术：CMOS
电信集成电路类型：TELECOM CIRCUIT温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：7 mm

GP2015/1G/FP2Q 数据手册

 浏览型号GP2015/1G/FP2Q的Datasheet PDF文件第4页浏览型号GP2015/1G/FP2Q的Datasheet PDF文件第5页浏览型号GP2015/1G/FP2Q的Datasheet PDF文件第6页浏览型号GP2015/1G/FP2Q的Datasheet PDF文件第8页浏览型号GP2015/1G/FP2Q的Datasheet PDF文件第9页浏览型号GP2015/1G/FP2Q的Datasheet PDF文件第10页 
GP2015  
Pin No.  
18  
Signal Name  
VDD (IO)  
PDn  
Input/Output  
Input  
Description  
Positive supply to the Digital Interface. (See Note 2)  
19  
Input  
Power-Down control input.  
A TTL compatible input, which when set to logic high, will  
disable ALL of the GP2015 functions, except the power-on  
reset block. Useful to reduce the total power consumption of  
the GP2015. If this feature is not required, the pin should be  
connected to 0V (VEE/GND).  
20  
21  
TEST  
Input  
Test control input - Disable PLL.  
A TTL compatible input, which when set to logic high, will  
disable the on-chip PLL, by disconnecting the divided-down  
VCO signal to the phase-detector. The VCO will free run at its  
upper range of frequency operation. If this feature is not  
required, the pin should be connected to 0V (VEE/GND).  
LD  
Output  
PLL Lock Detect output.  
A TTL compatible output, which indicates if the PLL is phase-  
locked to the PLL reference oscillator. Will become logic high  
only when phase-lock is achieved.  
22  
23  
VEE (DIG)  
AGC-  
Input  
Negative supply to the PLL and A to D converter.  
Output  
AGC Capacitor output - inverse phase.  
One side of a balanced output from the AGC block within IF  
Stage 3, to which an external capacitor is connected to set the  
AGC time-constant.  
24  
AGC+  
N/C  
Output  
AGC Capacitor output - true phase.  
One side of a balanced output from the AGC block within IF  
Stage 3, to which an external capacitor is connected to set the  
AGC time-constant.  
25  
26  
27  
Not connected. (See Note 4)  
V
CC (DIG)  
Input  
Input  
Positive supply to the PLL and A to D converter.  
REF 2  
10.000MHz PLL Reference signal input .  
Input to which an externally generated 10.000MHz PLL  
reference signal should be ac coupled, if an external PLL  
reference frequency source (e.g TCXO) is used (see fig. 6).  
If no external reference is used, this pin forms part of the on-  
chip PLL reference oscillator, in conjunction with an external  
10.000MHz crystal (see fig. 5).  
28  
REF 1  
Input  
PLL reference oscillator auxillary connection.  
Used in conjunction with Pin 27 (REF 2) to allow a 10.000MHz  
external crystal to provide the PLL reference signal if no  
external PLL reference frequency source (e.g TCXO) is used.  
This pin should NOT be connected if an external TCXO is  
being used (see fig. 5).  
29, 35  
VCC (RF)  
Input  
Input  
Positive supply to the RF input and Stage 1 IF mixer.  
Bothpinsareconnectedinternally,butmustbothbeconnected  
to VCC externally, to keep series inductance to a minimum.  
30, 31,  
33, 34  
VEE (RF)  
Negative supply to the RF input and Stage 1 IF mixer. The  
pins are all connected internally, but must ALL be connected  
to 0V (VEE/GND) externally, to keep series inductance to a  
minimum.  
7
1...45678910...24

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