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GM71VS17803CLJ-7 PDF预览

GM71VS17803CLJ-7

更新时间: 2024-02-04 01:29:02
品牌 Logo 应用领域
其他 - ETC 内存集成电路光电二极管动态存储器
页数 文件大小 规格书
9页 99K
描述
x8 EDO Page Mode DRAM

GM71VS17803CLJ-7 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.79
Is Samacsys:N访问模式:FAST PAGE WITH EDO
最长访问时间:70 ns其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH/SELF REFRESH; BATTERY BACKUP OPERATION
I/O 类型:COMMONJESD-30 代码:R-PDSO-J28
JESD-609代码:e0内存密度:16777216 bit
内存集成电路类型:EDO DRAM内存宽度:8
功能数量:1端口数量:1
端子数量:28字数:2097152 words
字数代码:2000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2MX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ28,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
刷新周期:2048自我刷新:YES
最大待机电流:0.00015 A子类别:DRAMs
最大压摆率:0.09 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

GM71VS17803CLJ-7 数据手册

 浏览型号GM71VS17803CLJ-7的Datasheet PDF文件第2页浏览型号GM71VS17803CLJ-7的Datasheet PDF文件第3页浏览型号GM71VS17803CLJ-7的Datasheet PDF文件第4页浏览型号GM71VS17803CLJ-7的Datasheet PDF文件第5页浏览型号GM71VS17803CLJ-7的Datasheet PDF文件第6页浏览型号GM71VS17803CLJ-7的Datasheet PDF文件第7页 
GM71V17803C  
GM71VS17803CL  
2,097,152 WORDS x 8 BIT  
CMOS DYNAMIC RAM  
Description  
Features  
The GM71V(S)17803C/CL is the new  
generation dynamic RAM organized 2,097,152  
x 8 bit. GM71V(S)17803C/CL has realized  
higher density, higher performance and various  
functions by utilizing advanced CMOS process  
technology. The GM71V(S)17803C/CL offers  
Extended Data out(EDO) Page Mode as a high  
speed access mode. Multiplexed address inputs  
permit the GM71V(S)17803C/CL to be  
packaged in standard 400 mil 28pin plastic SOJ,  
and standard 400mil 28pin plastic TSOP II. The  
package size provides high system bit densities  
and is compatible with widely available  
automated testing and insertion equipment.  
* 2,097,152 Words x 8 Bit Organization  
* Extended Data Out Mode Capability  
* Single Power Supply (3.3V+/-0.3V)  
* Fast Access Time & Cycle Time  
(Unit: ns)  
tRAC  
tCAC  
tRC  
tHPC  
50  
60  
70  
13  
15 104  
18 124  
84  
20  
25  
30  
GM71V(S)17803C/CL-5  
GM71V(S)17803C/CL-6  
GM71V(S)17803C/CL-7  
* Low Power  
Active : 396/360/324mW (MAX)  
Standby : 7.2mW (CMOS level : MAX)  
0.36mW (L-version : MAX)  
* RAS Only Refresh, CAS before RAS Refresh,  
Hidden Refresh Capability  
*All inputs and outputs TTL Compatible  
* 2048 Refresh Cycles/32ms  
* 2048 Refresh Cycles/128ms (L-version)  
* Self Refresh Operation (L-version)  
* Battery Back Up Operation (L-version)  
Pin Configuration  
28 SOJ  
28 TSOP II  
1
2
3
4
5
6
28  
27  
1
2
3
4
5
6
28  
27  
VCC  
VSS  
VCC  
VSS  
I/O0  
I/O1  
I/O7  
I/O0  
I/O1  
I/O7  
26 I/O6  
26 I/O6  
25  
24  
23  
25  
24  
23  
I/O2  
I/O3  
I/O5  
I/O4  
CAS  
I/O2  
I/O3  
I/O5  
I/O4  
CAS  
WE  
RAS  
NC  
WE  
7
22  
21  
20  
19  
18  
17  
16  
15  
7
22  
OE  
A9  
A8  
A7  
A6  
A5  
A4  
VSS  
OE  
RAS  
NC  
8
8
21 A9  
9
9
20  
A10  
A0  
A10  
A0  
A8  
10  
11  
12  
13  
14  
10  
11  
12  
13  
14  
19  
18  
17  
16  
15  
A7  
A6  
A5  
A4  
VSS  
A1  
A1  
A2  
A2  
A3  
A3  
VCC  
VCC  
(Top View)  
Rev 0.1 / Apr’01  

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