Datasheet > GM71S17403C(CL)

GM71S17403C(CL)

更新时间： 2022-01-19 19:43:00

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
10页	101K
描述
4Mx4\|3.3V\|2K\|5/6/7\|FP/EDO DRAM - 16M

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GM71S17403C(CL) 数据手册

GM71V17403C

GM71VS17403CL

WCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the

data sheet as electrical characteristics only; if tWCS>=tWCS(min), the cycles is an early write cycle

and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if

14.

RWD>=tRWD(min), the tCWD>=tCWD(min), and tAWD>=tAWD(min), or tCWD>=tCWD(min), tAWD>=

tAWD(min) and tCPW>=tCPW(min), the cycle is a read-modify-write and the data output will contain

data read from the selected cell; if neither of the above sets of conditions is satisfied, the

condition of the data out (at access time) is indeterminate.

These parameters are referenced to CAS leading edge in early write cycles and to WE leading

edge in delayed write or read-modify-write cycles.

15.

16.

tRASP defines RAS pulse width in EDO page mode cycles.

17.

18.

Access time is determined by the longest among tAA or tCAC or tACP.

The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the

4M x 4 are don't care during test mode. Test mode is set by performing a WE-and-CAS-before-

RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O

(I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data

output pin is a high state during test mode read cycle, then the device has passed. If they are not

equal, data output pin is a low state, then the device has failed. Refresh during test mode

operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test

mode and enter a normal operation mode, perform either a regular CAS-before-RAS refresh

cycle or RAS-only refresh cycle.

19. In a test mode read cycle, the value of tRAC, tAA, tCAC and tACP is delayed by 2ns to 5ns for the

specified value. These parameters should be specified in test mode cycles by adding the above

value to the specified value in this data sheet.

tHPC(min) can be achieved during a series of EDO page mode write cycles or EDO page mode

read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle(EDO

page mode mix cycle (1),(2)), minimum value of CAS cycle (tCAS + tCP + 2tT) becomes greater

than the specified tHPC(min) value. The value of CAS cycle time of mixed EDO page mode is

shown in EDO page mode mix cycle (1) and (2).

20.

Rev 0.1 / Apr’01

1...6 7 8910

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与GM71S17403C(CL)相关器件

型号	品牌	获取价格	描述	数据表
GM71S17403C-5	HYNIX	获取价格	4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
GM71S17403C-6	HYNIX	获取价格	4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
GM71S17403C-7	HYNIX	获取价格	4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
GM71S17403CL-5	HYNIX	获取价格	4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
GM71S17403CL-6	HYNIX	获取价格	4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
GM71S17403CL-7	HYNIX	获取价格	4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
GM71S17800C(CL)	ETC	获取价格	2Mx8\|5V\|2K\|5/6\|FP/EDO DRAM - 16M
GM71S17803C(CL)	ETC	获取价格	2Mx8\|5V\|2K\|5/6\|FP/EDO DRAM - 16M
GM71S18160C(CL)	ETC	获取价格	1Mx16\|5V\|1K\|5/6\|FP/EDO DRAM - 16M
GM71S18163C(CL)	ETC	获取价格	1Mx16\|5V\|1K\|5/6\|FP/EDO DRAM - 16M

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