Datasheet > GM71C17400C(CL)

GM71C17400C(CL)

更新时间： 2022-01-19 19:43:00

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
10页	102K
描述
4Mx4\|5V\|2K\|5/6/7\|FP/EDO DRAM - 16M

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GM71C17400C(CL) 数据手册

GM71C(S)17400C/CL

Notes:

1. AC Measurements assume tT =5ns.

2. An initial pause of 200us is required after power up followed by a minimum of eight

initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-

RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS

refresh cycles are required.

3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a

reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is

controlled exclusively by tCAC.

4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a

reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is

controlled exclusively by tAA.

5. Either tODD or tCDD must be satisfied.

6. Either tDZO or tDZC must be satisfied.

VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,

transition times are measured between VIH(min) and VIL(max).

8. Assume that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum

recommended value shown in this table, tRAC exceeds the value shown.

9. Measured with a load circuit equivalent to 2 TTL loads and 100pF. (VOH = 2.4V, VOL = 0.8V)

Assume that tRCD >=tRCD(max) and tRCD +

CAC(max) >= tRAD + AA(max).

10.

11. Assume that tRAD >=tRAD(max) and tRCD +

tCAC(max) <= tRAD + tAA(max).

12.

13.

Either tRCH or tRRH must be satisfied for a read cycles.

tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit condition

and are not referenced to output voltage levels.

14.

tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the

data sheet as electrical characteristics only; if tWCS>=tWCS(min), the cycle is an early write cycle

and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if

RWD>=tRWD(min), tCWD>=tCWD(min), and tAWD>=tAWD(min), or tCWD>=tCWD(min), tAWD>=

tAWD(min) and tCPW>=tCPW(min), the cycle is a read-modify-write and the data output will contain

data read from the selected cell; if neither of the above sets of conditions is satisfied, the

condition of the data out (at access time) is indeterminate.

15. These parameters are referenced to CAS leading edge in early write cycles and to WE leading

edge in delayed write or read-modify-write cycles.

RASP defines RAS pulse width in Fast page mode cycles.

16.

17.

Access time is determined by the longest among tAA or tCAC or tACP.

Rev 0.1 / Apr’01

1...5 6 789 10

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与GM71C17400C(CL)相关器件

型号	品牌	获取价格	描述	数据表
GM71C17400CJ	HYNIX	获取价格	4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
GM71C17400CJ-5	HYNIX	获取价格	x4 Fast Page Mode DRAM
GM71C17400CJ-6	HYNIX	获取价格	x4 Fast Page Mode DRAM
GM71C17400CJ-7	HYNIX	获取价格	x4 Fast Page Mode DRAM
GM71C17400CLJ-5	HYNIX	获取价格	4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
GM71C17400CLJ-6	HYNIX	获取价格	4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
GM71C17400CLJ-7	HYNIX	获取价格	4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
GM71C17400CLT-5	HYNIX	获取价格	4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
GM71C17400CLT-6	HYNIX	获取价格	4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
GM71C17400CLT-7	HYNIX	获取价格	4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM

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