Revision 3
Military ProASIC3/EL Low Power Flash FPGAs
with Flash*Freeze Technology
•
Architecture Supports Ultra-High Utilization
Features and Benefits
Advanced and Pro (Professional) I/Os††
Military Temperature Tested and Qualified
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 8 Banks per Chip
†
•
Each Device Tested from –55°C to 125°C
Firm-Error Immune
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and
•
Not Susceptible to Neutron-Induced Configuration Loss
†
Low Power
LVCMOS 2.5 V / 5.0 V Input
•
•
•
Dramatic Reduction in Dynamic and Static Power
1.2 V to 1.5 V Core and I/O Voltage Support for Low Power
•
•
Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II (A3PE3000L only)
†
Low Power Consumption in Flash*Freeze Mode Allows for
Instantaneous Entry To / Exit From Low-Power Flash*Freeze
ƒ
Mode
•
•
•
•
•
•
•
•
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay (A3PE3000L only)
Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)
Weak Pull-Up/-Down
•
•
Supports Single-Voltage System Operation
Low-Impedance Switches
High Capacity
•
•
•
250K to 3M System Gates
Up to 504 kbits of True Dual-Port SRAM
Up to 620 User I/Os
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the Military ProASIC 3EL Family
®
Reprogrammable Flash Technology
Clock Conditioning Circuit (CCC) and PLL
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
•
•
•
Six CCC Blocks—One Block with Integrated PLL in ProASIC3
and All Blocks with Integrated PLL in ProASIC3EL
Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V
systems) and 350 MHz (1.5 V systems)
Retains Programmed Design when Powered Off
High Performance
•
350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System
Performance
3.3 V, 66 MHz, 64-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit
PCI (1.2 V systems)
SRAMs and FIFOs
•
•
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
True Dual-Port SRAM (except ×18)
24 SRAM and FIFO Configurations with Synchronous
Operation:
– 250 MHz: For 1.2 V Systems
– 350 MHz: For 1.5 V Systems
In-System Programming (ISP) and Security
•
•
•
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
®
•
FlashLock to Secure FPGA Contents
High-Performance Routing Hierarchy
ARM® Processor Support in ProASIC3/EL FPGAs
•
•
•
Segmented, Hierarchical Routing and Clock Structure
High-Performance, Low-Skew Global Network
ARM Cortex™-M1 Soft Processor Available with or without
Debug
Table 1 • Military ProASIC3/EL Low-Power Devices
ProASIC3/EL Devices
ARM Cortex-M1 Devices
System Gates
A3P250
A3PE600L
A3P1000
A3PE3000L
1
M1A3P1000
M1A3PE3000L
250,000
600,000
13,824
108
24
1M
24,576
144
32
3M
75,264
504
112
1
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
6,144
36
8
FlashROM Kbits
1
1
1
2
Secure (AES) ISP
Yes
1
Yes
6
Yes
1
Yes
6
Integrated PLL in CCCs
VersaNet Globals
I/O Banks
18
4
18
18
18
8
4
8
Maximum User I/Os
68
270
154
620
Package Pins
VQFP
VQ100
PQFP
PQ208
FG144, FG484
FBGA
FG484
FG484, FG896
Notes:
1. Refer to the Cortex-M1 product brief for more information.
2. AES is not available for ARM-enabled ProASIC3/EL devices.
† A3P250 and A3P1000 support only 1.5 V core operation.
ƒ Flash*Freeze technology is not available for A3P250 or A3P1000.
††Pro I/Os are not available on A3P250 or A3P1000.
September 2012
I
© 2011 Microsemi Corporation
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