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FT245BL

更新时间: 2024-01-03 03:38:02
品牌 Logo 应用领域
飞特帝亚 - FTDI 外围集成电路先进先出芯片PC
页数 文件大小 规格书
24页 541K
描述
USB FIFO ( USB - Parallel ) I.C.

FT245BL 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:,Reach Compliance Code:compliant
风险等级:5.81Base Number Matches:1

FT245BL 数据手册

 浏览型号FT245BL的Datasheet PDF文件第2页浏览型号FT245BL的Datasheet PDF文件第3页浏览型号FT245BL的Datasheet PDF文件第4页浏览型号FT245BL的Datasheet PDF文件第6页浏览型号FT245BL的Datasheet PDF文件第7页浏览型号FT245BL的Datasheet PDF文件第8页 
FT245BL USB FIFO ( USB - Parallel ) I.C.  
3.0 Block Diagram ( simplified )  
VCC  
Send Immediate / WakeUP  
PWREN#  
3.3 Volt  
LDO  
Regulator  
FIFO Receive  
Buffer  
128 Bytes  
3V3OUT  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
USBDP  
Serial Interface  
FIFO  
Controller  
USB  
Transceiver  
USB  
Protocol Engine  
Engine  
( SIE )  
USBDM  
RD#  
WR  
RXF#  
TXE#  
FIFO Transmit  
Buffer  
384 Bytes  
USB DPLL  
3V3OUT  
EECS  
XTOUT  
XTIN  
48MHz  
EEPROM  
Interface  
EESK  
6MHZ  
Oscillator  
x8 Clock  
Multiplier  
EEDATA  
12MHz  
RESET  
GENERATOR  
GND  
RESET#  
RSTOUT#  
TEST  
3.1 Functional Block Descriptions  
3.3V LDO Regulator  
USB DPLL  
The 3.3V LDO Regulator generates the 3.3 volt  
reference voltage for driving the USB transceiver  
cell output buffers. It requires an external  
The USB DPLL cell locks on to the incoming NRZI  
USB data and provides separate recovered clock  
and data signals to the SIE block.  
decoupling capacitor to be attached to the 3V3OUT  
regulator output pin. It also provides 3.3V power to  
the RSTOUT# pin. The main function of this block  
is to power the USB Transceiver and the Reset  
Generator Cells rather than to power external logic.  
However, external circuitry requiring 3.3V nominal  
at a current of not greater than 5mA could also  
draw its power from the 3V3OUT pin if required.  
6MHz Oscillator  
The 6MHz Oscillator cell generates a 6MHz  
reference clock input to the x8 Clock multiplier from  
an external 6MHz crystal or ceramic resonator.  
x8 Clock Multiplier  
The x8 Clock Multiplier takes the 6MHz input  
from the Oscillator cell and generates a 12MHz  
reference clock for the SIE, USB Protocol Engine  
and FIFO controller blocks. It also generates a  
48MHz reference clock for the USB DPLL.  
USB Transceiver  
The USB Transceiver Cell provides the USB 1.1 /  
USB 2.0 full-speed physical interface to the USB  
cable. The output drivers provide 3.3 volt level slew  
rate control signalling, whilst a differential receiver  
and two single ended receivers provide USB data  
in, SEO and USB Reset condition detection.  
DS245BL Version 1.7  
© Future Technology Devices Intl. Ltd. 2005  
Page 5 of 24  

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