Datasheet > FS6370-01TR

FS6370-01TR

更新时间： 2024-02-28 14:11:45

品牌	Logo	应用领域
AMI		光电二极管
页数	文件大小	规格书
25页	1416K
描述
Clock Generator, CMOS, PDSO16,

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技术参数
数据手册

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FS6370-01TR 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.8	JESD-30 代码：	R-PDSO-G16
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3.3/5 V	认证状态：	Not Qualified
子类别：	Clock Generators	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

FS6370-01TR 数据手册

FS6370-01

EEPROM Programmable 3-PLL Clock Generator IC

For sequential read operations, the EEPROM has an in-

ternal address pointer that increments by one at the end

7.0 Cost Reduction Migration Path

of each read operation. The pointer directs the EEPROM

to transmit the next sequentially addressed data byte,

allowing the entire memory contents to be read in one

operation.

The FS6370 is compatible with the programmable regis-

ter-based FS6377 or a fixed-frequency ROM-based clock

generator. Attention should be paid to the board layout if

a migration path to either of these devices is desired.

6.2

Direct Register Programming

7.1

Programming Migration Path

The FS6370 control registers may be directly accessed

by simply using the FS6370 device address in the read or

write operations. The operation of the device will follow

the register values. The register map of the FS6370 is

identical to that of the EEPROM shown in Table 3.

The FS6370 supports the Random Read and Write pro-

cedures, as well as the Sequential Read and Write pro-

cedures described on Page 7.

If the design can support I²C programming overhead, a

cost reduction from the EEPROM-based FS6370 to the

Figure 5 shows the five pins that may not be compatible

between the various devices if programming of the

FS6370 or the FS6377 is desired.

Figure 5: FS6370 to FS6377

The device address for the FS6370 is:

VSS

SDA

VDD

SCL

(FS6370)

(FS6377)

(FS6370)

(FS6377)

PD/SCL

SEL_CD

CLK_A

VDD

(FS6370)

VSS

XIN

CLK_B

CLK_C

VSS

(FS6377)

OE/SDA

XOUT

(FS6370)

MODE

CLK_D

(FS6370)

VDD

(FS6377)

ADDR

(FS6377)

7.2

Non-Programming Migration Path

If the design has solidified on a particular EEPROM pro-

gramming pattern, the EEPROM pattern can be hard-

coded into a ROM-based device. For high-volume re-

quirements, a ROM-based device offers significant cost

savings over the FS6370. Contact an AMI Sales repre-

sentative for more detail.

1...3 4 567 8 9...25

中文翻译

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与FS6370-01TR相关器件

型号	品牌	获取价格	描述	数据表
FS6370-01-XTD	ONSEMI	获取价格	暂无描述
FS6370-01-XTD	AMI	获取价格	Clock Generator, CMOS, PDSO16,
FS6370-01-XTP	AMI	获取价格	Clock Generator, CMOS, PDSO16,
FS6377	ONSEMI	获取价格	Programmable 3-PLL Clock Generator IC
FS6377-01	AMI	获取价格	Programmable 3-PLL Clock Generator IC
FS6377-01G	AMI	获取价格	Programmable 3-PLL Clock Generator IC
FS6377-01G-XTD	ONSEMI	获取价格	Programmable 3-PLL Clock Generator IC
FS6377-01G-XTP	ONSEMI	获取价格	Programmable 3-PLL Clock Generator IC
FS6377-01I	ONSEMI	获取价格	暂无描述
FS6377-01IG	AMI	获取价格	Clock Generator, 150MHz, CMOS, PDSO16, 0.150 INCH, GREEN, SOIC-16

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