Datasheet > FS6370-01TR

FS6370-01TR

更新时间： 2024-01-10 03:22:44

品牌	Logo	应用领域
AMI		光电二极管
页数	文件大小	规格书
25页	1416K
描述
Clock Generator, CMOS, PDSO16,

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技术参数
数据手册

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FS6370-01TR 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.8	JESD-30 代码：	R-PDSO-G16
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3.3/5 V	认证状态：	Not Qualified
子类别：	Clock Generators	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

FS6370-01TR 数据手册

FS6370-01

EEPROM Programmable 3-PLL Clock Generator IC

Table 1: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI^U= Input with Internal Pull-Up; DI_D= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,

DO = Digital Output; P = Power/Ground; # = Active Low pin

TYPE

NAME

DESCRIPTION

VSS

SEL_CD

Ground

DI^U

Selects one of two programmed PLL C, Mux C/D, and Post Divider C/D combinations

Power-Down Input (Run Mode) or

DI^U

PD/SCL

Serial Interface Clock Input (Program Mode)

VSS

XIN

XOUT

Ground

Crystal Oscillator Feedback

Crystal Oscillator Drive

Output Enable Input (Run Mode) or

DI^UO

OE/SDA

Serial Interface Data Input/Output (Program Mode)

DI^U

VDD

MODE

CLK_D

VSS

CLK_C

CLK_B

VDD

Power Supply (5V to 3.3V)

Selects either Program Mode (low) or Run Mode (high)

D Clock Output

Ground

C Clock Output

B Clock Output

Power Supply (5V to 3.3V)

A Clock Output

CLK_A

VDD

Power Supply (5V to 3.3V)

The PFD controls the frequency of the VCO (f_VCO

)

through the charge pump and loop filter. The VCO pro-

vides a high-speed, low noise, continuously variable fre-

quency clock source for the PLL. The output of the VCO

is fed back to the PFD through the Feedback Divider (the

modulus is denoted by N_F) to close the loop.

3.0 Functional Block Description

3.1

Phase Locked Loops

Each of the three on-chip phase-locked loops (PLLs) is a

standard phase- and frequency-locked loop architecture

that multiplies a reference frequency to a desired fre-

quency by a ratio of integers. This frequency multiplica-

tion is exact.

Figure 3: PLL Block Diagram

LFTC

As shown in Figure 3, each PLL consists of a Reference

Divider, a Phase-Frequency Detector (PFD), a charge

pump, an internal loop filter, a Voltage-Controlled Oscil-

lator (VCO), and a Feedback Divider.

During operation, the reference frequency (f_REF), gener-

ated by the on-board crystal oscillator, is first reduced by

the Reference Divider. The divider value is often referred

to as the modulus, and is denoted as N_Rfor the Refer-

ence Divider. The divided reference is fed into the PFD.

Loop

REFDIV[7:0]

Filter

f_REF

Reference

Divider

f_VCO

Phase-

Frequency

Detector

Voltage

Controlled

Oscillator

(N_R)

Charge

Pump

DOWN

FBKDIV[10:0]

f_PD

Feedback

Divider (N_F)

123 4 5 6 7...25

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与FS6370-01TR相关器件

型号	品牌	描述	获取价格	数据表
FS6370-01-XTD	ONSEMI	暂无描述	获取价格
FS6370-01-XTD	AMI	Clock Generator, CMOS, PDSO16,	获取价格
FS6370-01-XTP	AMI	Clock Generator, CMOS, PDSO16,	获取价格
FS6377	ONSEMI	Programmable 3-PLL Clock Generator IC	获取价格
FS6377-01	AMI	Programmable 3-PLL Clock Generator IC	获取价格
FS6377-01G	AMI	Programmable 3-PLL Clock Generator IC	获取价格

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