Datasheet > FS6282-03

FS6282-03

更新时间： 2024-02-11 19:43:47

品牌	Logo	应用领域
其他 - ETC		时钟发生器光电二极管
页数	文件大小	规格书
5页	53K
描述
DUAL PLL CLOCK GENERATOR IC

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技术参数
数据手册

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FS6282-03 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.84	Is Samacsys：	N
JESD-30 代码：	R-PDSO-G8	端子数量：	8
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Clock Generators
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

FS6282-03 数据手册

FS6282

AMERICAN MICROSYSTEMS, INC.

Dual PLL Clock Generator IC

October 1999

Table 5: DC Electrical Specifications

Unless otherwise stated, V_DD= 3.3V ± 10%, no load on any output, and ambient temperature range T_A= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization

data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

TYP.

MAX.

UNITS

Overall

Supply Current, Dynamic, with Loaded

Outputs

I_DD

f_XTAL= 13.5MHz; C_L= 10pF, V_DD= 3.6V

Crystal Oscillator

As seen by a crystal connected to XIN and

XOUT

Crystal Loading Capacitance

Clock Outputs (CLKA, CLKB)

C_L(xtal)

z_OH

z_OL

V_O= 0.1V_DD; output driving high

V_O= 0.1V_DD; output driving low

V_O= 0V; shorted for 30s, max.

V_O= 3.3V; shorted for 30s, max.

Ω

Output Impedance *

Short Circuit Source Current *

Short Circuit Sink Current *

I_OSH

I_OSL

-35

Table 6: AC Timing Specifications

Unless otherwise stated, V_DD= 3.3V ± 10%, no load on any output, and ambient temperature range T_A= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization

data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

TYP.

MAX.

UNITS

Overall

Synthesis Error

(unless otherwise noted in Frequency Table)

ppm

Clock Outputs (CLKA, CLKB, CLKC)

Ratio of high pulse width (as measured from rising edge to next falling

edge at V_DD/2) to one clock period

Duty Cycle *

From rising edge to next rising edge at V_DD/2, C_L=

10pF

t_j(∆P)

Jitter, Period (peak-peak) *

300

Rise Time *

Fall Time *

t_r

t_f

V_DD= 3.3V; V_O= 0.3V to 3.0V; C_L= 10pF

V_DD= 3.3V; V_O= 3.0V to 0.3V; C_L= 10pF

2.5

10.1.99

ISO9001

1 234 5

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