Datasheet > FM25V40-GCTR

FM25V40-GCTR

更新时间： 2022-02-26 11:02:34

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
23页	851K
描述
4-Mbit (512 K Ã 8) Serial (SPI) F-RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

FM25V40-GCTR 数据手册

PRELIMINARY

FM25V40

Pinouts

Figure 1. 8-pin SOIC pinout

HOLD

SCK

Top View

not to scale

Figure 2. 8-pin TDFN pinout

HOLD

SCK

EXPOSED

PAD

Top View

not to scale

Pin Definitions

Pin Name

I/O Type

Description

Input

Chip Select. This active LOW input activates the device. When HIGH, the device enters low-power

standby mode, ignores other inputs, and the output is tristated. When LOW, the device internally

activates the SCK signal. A falling edge on CS must occur before every opcode.

SCK

SI^[1]

SO^[1]

Input

Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising

edge and outputs occur on the falling edge. Because the device is synchronous, the clock

frequency may be any value between 0 and 40 MHz and may be interrupted at any time.

Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of

SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD

specifications.

Output

Input

Serial Output. This is the data output pin. It is driven during a read and remains tristated at all

other times including when HOLD is LOW. Data transitions are driven on the falling edge of the

serial clock.

Write Protect. This Active LOW pin prevents write operation to the Status Register when WPEN

is set to ‘1’. This is critical because other write protection features are controlled through the Status

Protection” on page 7. This pin must be tied to V_DDif not used.

HOLD

Input

HOLD Pin. The HOLD pin is used when the host CPU must interrupt a memory operation for

another task. When HOLD is LOW, the current operation is suspended. The device ignores any

transition on SCK or CS. All transitions on HOLD must occur while SCK is LOW. This pin must be

tied to V_DDif not used.

V_SS

V_DD

Power supply Ground for the device. Must be connected to the ground of the system.

Power supply Power supply input to the device.

EXPOSED PAD No connect The EXPOSED PAD on the bottom of 8-pin TDFN package is not connected to the die. The

EXPOSED PAD should be left floating.

Note

1. SI may be connected to SO for a single pin data interface.

Document Number: 001-87288 Rev. *A

Page 3 of 23

1 234 5 6 7...23

中文翻译

下载PDF

与FM25V40-GCTR相关器件

型号	品牌	描述	获取价格	数据表
FM25VN02-DG	RAMTRON	256Kb Serial 3V F-RAM Memory	获取价格
FM25VN02-DGTR	RAMTRON	256Kb Serial 3V F-RAM Memory	获取价格
FM25VN02-G	RAMTRON	256Kb Serial 3V F-RAM Memory	获取价格
FM25VN02-GTR	RAMTRON	256Kb Serial 3V F-RAM Memory	获取价格
FM25VN05-G	RAMTRON	512Kb Serial 3V F-RAM Memory	获取价格
FM25VN05-G	CYPRESS	512Kb Serial 3V F-RAM Memory	获取价格