FM25C160C-G

更新时间： 2024-02-01 00:42:25

品牌	Logo	应用领域
铁电 - RAMTRON		存储
页数	文件大小	规格书
13页	279K
描述
16Kb Serial 5V F-RAM Memory

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中文翻译

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技术参数
数据手册

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FM25C160C-G 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Contact Manufacturer	零件包装代码：	DIP
包装说明：	DIP,	针数：	8
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.8
最大时钟频率 (fCLK)：	2.1 MHz	JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e0	长度：	9.817 mm
内存密度：	16384 bit	内存集成电路类型：	EEPROM
内存宽度：	8	功能数量：	1
端子数量：	8	字数：	2048 words
字数代码：	2000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	5.08 mm	串行总线类型：	SPI
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
最长写入周期时间 (tWC)：	10 ms	Base Number Matches：	1

FM25C160C-G 数据手册

FM25C160C - 16Kb 5V SPI F-RAM

WRSR – Write Status Register

RDSR - Read Status Register

The RDSR command allows the bus master to verify

the contents of the Status register. Reading Status

provides information about the current state of the

write protection features. Following the RDSR op-

code, the FM25C160C will return one byte with the

contents of the Status register. The Status register is

described in detail in a later section.

The WRSR command allows the user to select

certain write protection features by writing a byte to

the Status register. Prior to issuing a WRSR

command, the /WP pin must be high or inactive. Note

that on the FM25C160C, /WP only prevents writing

to the Status register, not the memory array. Prior to

sending the WRSR command, the user must send a

WREN command to enable writes. Note that

executing a WRSR command is a write operation and

therefore clears the Write Enable Latch. The bus

timing for RDSR and WRSR are shown below.

Figure 7. RDSR Bus Timing

Figure 8. WRSR Bus Timing

are nonvolatile (shaded yellow). The WEL flag

Status Register & Write Protection

indicates the state of the Write Enable Latch. This bit

is internally set by the WREN command and is

cleared by terminating a write cycle (/CS high) or by

using the WRDI command.

The write protection features of the FM25C160C are

multi-tiered. First, a WREN op-code must be issued

prior to any write operation. Assuming that writes are

enabled using WREN, writes to memory are

controlled by the Status register. As described above,

writes to the status register are performed using the

WRSR command and subject to the /WP pin. The

Status register is organized as follows.

BP1 and BP0 are memory block write protection bits.

They specify portions of memory that are write

protected as shown in the following table.

Table 3. Block Memory Write Protection

Table 2. Status Register

BP1

BP0 Protected Address Range

Bit

BP1

BP0

None

Name WPEN

WEL

600h to 7FFh (upper ¼)

400h to 7FFh (upper ½)

000h to 7FFh (all)

Bits 0 and 4-6 are fixed at 0 and cannot be modified.

Note that bit 0 (/RDY in EEPROMs) is wired low

since F-RAM writes have no delay and the memory

is never busy. All EEPROMs use Ready to indicate

whether a write cycle is complete or not. The WPEN,

BP1 and BP0 control write protection features. They

Rev. 1.1

July 2011

Page 6 of 13

1...3 4 567 8 9...13

中文翻译

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与FM25C160C-G相关器件

型号	品牌	获取价格	描述	数据表
FM25C160C-GTR	RAMTRON	获取价格	16Kb Serial 5V F-RAM Memory
FM25C160-G	RAMTRON	获取价格	Memory Circuit, 2KX8, CMOS, PDSO8, GREEN, MS-012AA, SOIC-8
FM25C160-GA	RAMTRON	获取价格	16Kb FRAM Serial Memory
FM25C160-GTR	RAMTRON	获取价格	Memory Circuit, 2KX8, CMOS, PDSO8, GREEN, MS-012AA, SOIC-8
FM25C160-P	ETC	获取价格	IC 16K SERIAL FRAM
FM25C160-S	ETC	获取价格	IC-SM-16K SERIAL FRAM
FM25C160-STR	RAMTRON	获取价格	Memory Circuit, 2KX8, CMOS, PDSO8, MS-012AA, SOIC-8
FM25C160U	FAIRCHILD	获取价格	16K-Bit SPI⑩ Interface Serial CMOS EEPROM
FM25C160UE	FAIRCHILD	获取价格	16K-Bit SPI⑩ Interface Serial CMOS EEPROM
FM25C160UEM8	ETC	获取价格	SPI Serial EEPROM

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