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FM24VN01-G PDF预览

FM24VN01-G

更新时间: 2024-02-06 22:14:29
品牌 Logo 应用领域
铁电 - RAMTRON 光电二极管内存集成电路
页数 文件大小 规格书
16页 334K
描述
Memory Circuit, 16KX8, CMOS, PDSO8, GREEN, MS-012AA, SOIC-8

FM24VN01-G 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:unknownHTS代码:8542.32.00.71
风险等级:5.84JESD-30 代码:R-PDSO-G8
长度:4.9 mm内存密度:131072 bit
内存集成电路类型:MEMORY CIRCUIT内存宽度:8
功能数量:1端子数量:8
字数:16384 words字数代码:16000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:16KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

FM24VN01-G 数据手册

 浏览型号FM24VN01-G的Datasheet PDF文件第1页浏览型号FM24VN01-G的Datasheet PDF文件第3页浏览型号FM24VN01-G的Datasheet PDF文件第4页浏览型号FM24VN01-G的Datasheet PDF文件第5页浏览型号FM24VN01-G的Datasheet PDF文件第6页浏览型号FM24VN01-G的Datasheet PDF文件第7页 
FM24V01 - 128Kb I2C FRAM  
Address  
Latch  
2K x 64  
FRAM Array  
Counter  
8
SDA  
Serial to Parallel  
Converter  
Data Latch  
8
SCL  
WP  
Control Logic  
Device ID and  
Serial Number  
A0-A2  
Figure 1. FM24V01 Block Diagram  
Pin Description  
Pin Name  
Type  
Pin Description  
A0-A2  
Input  
Device Select Address 0-2: These pins are used to select one of up to 8 devices of  
the same type on the same two-wire bus. To select the device, the address value on  
the two pins must match the corresponding bits contained in the slave address. The  
address pins are pulled down internally.  
SDA  
I/O  
Serial Data/Address: This is a bi-directional pin for the two-wire interface. It is  
open-drain and is intended to be wire-OR’d with other devices on the two-wire bus.  
The input buffer incorporates a Schmitt trigger for noise immunity and the output  
driver includes slope control for falling edges. An external pull-up resistor is  
required.  
SCL  
WP  
Input  
Input  
Serial Clock: The serial clock pin for the two-wire interface. Data is clocked out of  
the part on the falling edge, and into the device on the rising edge. The SCL input  
also incorporates a Schmitt trigger input for noise immunity.  
Write Protect: When tied to VDD, addresses in the entire memory map will be write-  
protected. When WP is connected to ground, all addresses may be written. This pin  
is pulled down internally.  
VDD  
VSS  
Supply  
Supply  
Supply Voltage  
Ground  
Rev. 1.0  
May 2010  
Page 2 of 16  

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