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FIN1048M PDF预览

FIN1048M

更新时间: 2024-09-29 20:27:11
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管接口集成电路
页数 文件大小 规格书
6页 253K
描述
3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver, SO 16L NB, 4800-RAIL

FIN1048M 技术参数

是否无铅: 不含铅生命周期:Obsolete
Reach Compliance Code:compliantFactory Lead Time:1 week
风险等级:5.66Is Samacsys:N
Base Number Matches:1

FIN1048M 数据手册

 浏览型号FIN1048M的Datasheet PDF文件第2页浏览型号FIN1048M的Datasheet PDF文件第3页浏览型号FIN1048M的Datasheet PDF文件第4页浏览型号FIN1048M的Datasheet PDF文件第5页浏览型号FIN1048M的Datasheet PDF文件第6页 
September 2001  
Revised August 2003  
FIN1048  
3.3V LVDS 4-Bit Flow-Through  
High Speed Differential Receiver  
General Description  
Features  
Greater than 400Mbs data rate  
This quad receiver is designed for high speed interconnect  
utilizing Low Voltage Differential Signaling (LVDS) technol-  
ogy. The receiver translates LVDS levels, with a typical dif-  
ferential input threshold of 100mV, to LVTTL signal levels.  
LVDS provides low EMI at ultra low power dissipation even  
at high frequencies. This device is ideal for high speed  
transfer of clock and data.  
Flow-through pinout simplifies PCB layout  
3.3V power supply operation  
0.4ns maximum differential pulse skew  
2.5ns maximum propagation delay  
Low power dissipation  
The FIN1048 can be paired with its companion driver, the  
FIN1047, or any other LVDS driver.  
Power-Off protection  
Fail safe protection for open-circuit, shorted and termi-  
nated conditions  
Meets or exceeds the TIA/EIA-644 LVDS standard  
Pin compatible with equivalent RS-422 and LVPECL  
devices  
16-Lead SOIC and TSSOP packages save space  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN1048M  
M16A  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
FIN1048MTC  
MTC16  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Name  
Description  
R
OUT1, ROUT2, ROUT3, ROUT4 LVTTL Data Outputs  
RIN1+, RIN2+, RIN3+, RIN4+  
RIN1, RIN2, RIN3, RIN4−  
EN  
Non-Inverting LVDS Inputs  
Inverting LVDS Inputs  
Driver Enable Pin  
EN  
VCC  
GND  
Inverting Driver Enable Pin  
Power Supply  
Ground  
Function Table  
Inputs  
Outputs  
RIN+  
ROUT−  
ROUT  
EN  
EN  
H
L or Open  
L or Open  
H
L
L
H
L
H
H
H
X
L or Open Fail Safe Condition  
H
Z
Z
H
X
X
X
X
X
L or Open  
H = HIGH Logic Level  
Z = High Impedance  
L = LOW Logic Level  
Fail Safe = Open, Shorted, Terminated  
X = Don’t Care  
© 2003 Fairchild Semiconductor Corporation  
DS500588  
www.fairchildsemi.com  

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