Preliminary
September 2001
Revised September 2001
FIN1101
LVDS Single Port High Speed Repeater
(Preliminary)
General Description
Features
■ Greater than 800 Mbps full differential path
This single port repeater is designed for high speed inter-
connects utilizing Low Voltage Differential Signaling
(LVDS) technology. It accepts and outputs LVDS levels
with a typical differential output swing of 350 mV which pro-
vides low EMI at ultra low power dissipation even at high
frequencies. It can directly accept LVPECL, HSTL, and
SSTL-2 for translating directly to LVDS.
■ 3.5 ps max random jitter and 135 ps max deterministic
jitter
■ 3.3V power supply operation
■ Wide rail-to-rail common mode range
■ Ultra low power consumption
■ LVDS receiver inputs accept LVPECL, HSTL, and
SSTL-2 directly
■ Power off protection
■ 6 kV HBM ESD protection
■ Meets or exceed the TA/EIA-644-A LVDS standard
■ Packaged in 8-pin SOIC and US8 (Preliminary)
■ Open circuit, shorted, and terminated fail safe protection
Ordering Code:
Order Number Package Number
Package Description
FIN1101M
FIN1101K8
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
8-Lead US8, 0.7mm x 3.1mm x 2.0mm
MAB08A
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Functional Diagram
Pin Descriptions
Function Table
Pin Name
RIN+
Description
Inputs
Outputs
Non-Inverting LVDS Inputs
Inverting LVDS Inputs
Non-Inverting Driver Outputs
Inverting Driver Outputs
Driver Enable Pin
RIN+
RIN−
DOUT+
DOUT−
EN
RIN−
H
H
L
L
H
L
L
H
L
DOUT+
DOUT−
EN
H
H
H
Fail Safe Case
H
Z
L or OPEN
X
X
Z
VCC
Power Supply
H = HIGH Logic Level
L = LOW Logic Level
X = Don't Care
GND
Ground
Z = High Impedance
© 2001 Fairchild Semiconductor Corporation
DS500654
www.fairchildsemi.com