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FIN1048MX_NL PDF预览

FIN1048MX_NL

更新时间: 2024-09-28 12:57:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 252K
描述
Line Receiver, 4 Func, 4 Rcvr, PDSO16, 0.150 INCH, MS-012, SOIC-16

FIN1048MX_NL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.46输入特性:DIFFERENTIAL
接口集成电路类型:LINE RECEIVER接口标准:EIA-644; TIA-644
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:9.9 mm湿度敏感等级:1
功能数量:4端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
最大输出低电流:0.008 A封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大接收延迟:2.5 ns
接收器位数:4座面最大高度:1.75 mm
子类别:Line Driver or Receivers最大压摆率:15 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

FIN1048MX_NL 数据手册

 浏览型号FIN1048MX_NL的Datasheet PDF文件第2页浏览型号FIN1048MX_NL的Datasheet PDF文件第3页浏览型号FIN1048MX_NL的Datasheet PDF文件第4页浏览型号FIN1048MX_NL的Datasheet PDF文件第5页浏览型号FIN1048MX_NL的Datasheet PDF文件第6页 
September 2001  
Revised August 2003  
FIN1048  
3.3V LVDS 4-Bit Flow-Through  
High Speed Differential Receiver  
General Description  
Features  
Greater than 400Mbs data rate  
This quad receiver is designed for high speed interconnect  
utilizing Low Voltage Differential Signaling (LVDS) technol-  
ogy. The receiver translates LVDS levels, with a typical dif-  
ferential input threshold of 100mV, to LVTTL signal levels.  
LVDS provides low EMI at ultra low power dissipation even  
at high frequencies. This device is ideal for high speed  
transfer of clock and data.  
Flow-through pinout simplifies PCB layout  
3.3V power supply operation  
0.4ns maximum differential pulse skew  
2.5ns maximum propagation delay  
Low power dissipation  
The FIN1048 can be paired with its companion driver, the  
FIN1047, or any other LVDS driver.  
Power-Off protection  
Fail safe protection for open-circuit, shorted and termi-  
nated conditions  
Meets or exceeds the TIA/EIA-644 LVDS standard  
Pin compatible with equivalent RS-422 and LVPECL  
devices  
16-Lead SOIC and TSSOP packages save space  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN1048M  
M16A  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
FIN1048MTC  
MTC16  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Name  
Description  
R
OUT1, ROUT2, ROUT3, ROUT4 LVTTL Data Outputs  
RIN1+, RIN2+, RIN3+, RIN4+  
RIN1, RIN2, RIN3, RIN4−  
EN  
Non-Inverting LVDS Inputs  
Inverting LVDS Inputs  
Driver Enable Pin  
EN  
VCC  
GND  
Inverting Driver Enable Pin  
Power Supply  
Ground  
Function Table  
Inputs  
Outputs  
RIN+  
ROUT−  
ROUT  
EN  
EN  
H
L or Open  
L or Open  
H
L
L
H
L
H
H
H
X
L or Open Fail Safe Condition  
H
Z
Z
H
X
X
X
X
X
L or Open  
H = HIGH Logic Level  
Z = High Impedance  
L = LOW Logic Level  
Fail Safe = Open, Shorted, Terminated  
X = Don’t Care  
© 2003 Fairchild Semiconductor Corporation  
DS500588  
www.fairchildsemi.com  

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