FDMF6821A
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min.
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
Max.
6.0
Unit
V
VCIN
VDRV
Supply Voltage
Referenced to CGND
Referenced to CGND
Referenced to CGND
Referenced to CGND
Referenced to CGND
Referenced to CGND
Referenced to CGND
Referenced to PGND, CGND
Drive Voltage
6.0
V
VDISB#
VPWM
VSMOD#
VGL
Output Disable
6.0
V
PWM Signal Input
Skip Mode Input
6.0
V
6.0
V
Low Gate Manufacturing Test Pin
Thermal Warning Flag
6.0
V
VTHWN#
6.0
V
VIN
Power Input
25.0
V
VBOOT
Bootstrap Supply
Referenced to VSWH, PHASE
Referenced to CGND
−0.3
−0.3
6.0
V
V
25.0
VGH
High Gate Manufacturing Test Pin
Referenced to VSWH, PHASE
Referenced to CGND
−0.3
−0.3
6.0
V
V
25.0
VPHS
VSWH
PHASE
Referenced to CGND
−0.3
25.0
V
Switch Node Input
Referenced to PGND, CGND (DC Only)
Referenced to PGND, <20 ns
−0.3
−8.0
25.0
28.0
V
V
VBOOT
Bootstrap Supply
Referenced to VDRV
22.0
25.0
7.0
60
V
V
Referenced to VDRV, <20 ns
ITHWN#
IO(AV)
THWN# Sink Current
−0.1
mA
A
(1)
Output Current
f
f
= 300 kHz, V = 12 V, V = 1.0 V
IN O
SW
= 1 MHz, V = 12 V, V = 1.0 V
55
SW
IN
O
Junction−to−PCB Thermal Resistance
2.7
°C/W
°C
qJPCB
T
A
Ambient Temperature Range
−40
+125
T
Maximum Junction Temperature
+150
+150
°C
°C
V
J
TSTG
Storage Temperature Range
−55
600
ESD
Electrostatic Discharge Protection
Human Body Model, JESD22−A114
Charged Device Model, JESD22−C101
2500
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
is rated using ON Semiconductor’s DrMOS evaluation board, at T = 25°C, with natural convection cooling. This rating is limited by
O(AV)
A
the peak DrMOS temperature, T = 150°C, and varies depending on operating conditions and PCB layout. This rating can be changed with
J
different application settings.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCIN
Parameter
Min.
4.5
Typ.
5.0
Max.
5.5
Unit
V
Control Circuit Supply Voltage
Gate Drive Circuit Supply Voltage
Output Stage Supply Voltage
VDRV
VIN
4.5
5.0
5.5
V
3.0
12.0
16.0
(Note 2)
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. Operating at high V can create excessive AC overshoots on the VSWH−to−GND and BOOT−to−GND nodes during MOSFET switching
IN
transients. For reliable DrMOS operation, VSWH−to−GND and BOOT−to−GND must remain at or below the Absolute Maximum Ratings
shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional
information.
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