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FD080H02A5B PDF预览

FD080H02A5B

更新时间: 2024-01-30 07:44:36
品牌 Logo 应用领域
威世 - VISHAY 二极管
页数 文件大小 规格书
3页 97K
描述
Rectifier Diode, 1 Phase, 1 Element, 600V V(RRM), Silicon, DIE-2

FD080H02A5B 技术参数

生命周期:Obsolete零件包装代码:DIE
包装说明:S-XUUC-N1针数:2
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8541.10.00.40风险等级:5.75
Is Samacsys:N应用:GENERAL PURPOSE
外壳连接:CATHODE配置:SINGLE
二极管元件材料:SILICON二极管类型:RECTIFIER DIODE
最大正向电压 (VF):0.8 VJESD-30 代码:S-XUUC-N1
元件数量:1相数:1
端子数量:1封装主体材料:UNSPECIFIED
封装形状:SQUARE封装形式:UNCASED CHIP
认证状态:Not Qualified最大重复峰值反向电压:600 V
最大反向恢复时间:0.026 µs子类别:Rectifier Diodes
表面贴装:YES端子形式:NO LEAD
端子位置:UPPERBase Number Matches:1

FD080H02A5B 数据手册

 浏览型号FD080H02A5B的Datasheet PDF文件第2页浏览型号FD080H02A5B的Datasheet PDF文件第3页 
Bulletin I0533J rev. A 04/06  
FD080H02A5F  
FRED Die in Wafer Form  
200V  
VF = 0.9V  
(max.)  
z 100% Tested at Probe c  
z Available in Tape and Reel (upon request)  
z Chip Pack, and Sawn on Film d  
5" Wafer  
Electrical Characteristics (@ T = 25°C)  
J
Parameter  
Description  
Typical Forward Voltage  
Typical Forward Voltage  
Typical Forward Voltage  
Min  
–––  
–––  
–––  
Typ  
0.83  
0.74  
0.74  
–––  
Max  
0.9V  
0.8  
Test Conditions  
VFM  
VFM  
VFM  
VRRM  
IRM  
trr  
TJ = 25°C, IF = 3A  
3)  
3)  
4)  
TJ = 25°C, IF = 1A  
–––  
–––  
3 μA  
–––  
–––  
TJ = 25°C, IF = 1A  
Minimum Reverse Breakdown Voltage 600v  
TJ = 25°C, IRRM = 100μA  
TJ = 25°C, VRRM = 200V  
IF = 1A, di/dt = 100A/μs, VR = 30v  
Max. Reverse Leakage Current  
Typ. Reverse Recovery Time  
Typ. Reverse Recovery Time  
–––  
–––  
–––  
–––  
26ns  
21ns  
4)  
trr  
IF = 3A, di/dt = 200A/μs, VR = 160v 3)  
Mechanical Data  
Nominal Back Metal Composition, Thickness:  
Nominal Front Metal Composition, Thickness:  
Dimensions:  
Cr-Ni-Ag ( 1kA-2kA-3kA)  
99%Al, 1%Si (3microns)  
0.080" x 0.080" (see drawing)  
125 mm  
Wafer Diameter:  
Wafer Thickness:  
14 mils  
Scribe Line Width  
66 ±10 μm  
Reject Ink Dot Size  
0.25 mm Diameter Minimum  
Store in original container, in dessicated  
nitrogen, with no contamination  
For optimum electrical results, die attach  
temperature should not exceed 300 °C  
Recommended Storage Environment:  
Recommended Die Attach Conditions:  
Reference Packaged Part  
IRM, trr and RthJC/ RthJA data refer to packed die in TO220  
Die Outline  
NOTES:  
40 (1.57)  
Wafer flat alligned with  
side b of the die  
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (MILS).  
2. CONTROLLING DIMENSION (INCH):  
0.35 ± 0.01  
a
c
(14 ± 0.4)  
3. DIMENSIONS AND TOLERANCES:  
a = 2.032 +0, - 0.01  
(80 +0, - 0.4)  
b = 2.032 +0, - 0.01  
(80 +0, - 0.4)  
C
c = 1.604 +0, - 0.01  
(63.14 +0, - 0.4)  
d = 1.604 +0, - 0.01  
(63.14 +0, - 0.4)  
A
4. LETTER DESIGNATION:  
A = Anode (Top Metal)  
C = Cathode (Back Metal)  
5. SAWING:  
Recommended Blade  
SEMITEC S1025 QS00 Blade  
Ø
125 (4.92)  
Note:  
1) The above data sheet is based on IR sample testing under certain predetermined and assumed conditions, and is  
provided for illustration purposes only. Customers are encouraged to perform testing in actual proposed packaged  
and use conditions. IR die products are tested using IR-based quality assurance procedures and are manufactured  
using IR’s established processes. Programs for customer-specified testing are available upon request. IR has  
experienced assembly yields of generally 95% or greater for individual die; however, customer’s results may vary.  
Estimates such as those described and set forth in this data sheet for semiconductor die will vary depending on a  
number of packaging, handling, use and other factors. Sold die may not perform on an equivalent basis to standard  
package products and are therefore offered with a limited warranty as described in IR’s applicable standard terms  
and conditions of sale. All IR die sales are subject to IR’s applicable standard terms and conditions of sale, which  
are available upon request.  
2) Part number shown is for die in waveform. Contact factory for these other options.  
3) V and t limits refer to packaed devices in TO-220 unless otherwise stated.  
rr  
F
4) V and t limits refer to wafer level  
rr  
F
Document Number: 93762  
www.vishay.com  
1

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