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EVAL-CONTROLBRD25

更新时间： 2024-11-24 04:55:19
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 576K
描述
2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70

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EVAL-CONTROLBRD25 数据手册

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2.35 V to 5.25 V, 1 MSPS,  
a
12-/10-/8-Bit ADCs in 6-Lead SC70  
AD7476A/AD7477A/AD7478A*  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Fast Throughput Rate: 1 MSPS  
Specified for VDD of 2.35 V to 5.25 V  
Low Power:  
V
DD  
3.6 mW Typ at 1 MSPS with 3 V Supplies  
12.5 mW Typ at 1 MSPS with 5 V Supplies  
Wide Input Bandwidth:  
12-/10-/8-BIT  
SUCCESSIVE-  
APPROXIMATION  
ADC  
V
T/H  
IN  
71 dB SNR at 100 kHz Input Frequency  
Flexible Power/Serial Clock Speed Management  
No Pipeline Delays  
High Speed Serial Interface  
SPI®/QSPI™/MICROWIRE™/DSP Compatible  
Standby Mode: 1 ␮A Max  
SCLK  
SDATA  
CS  
CONTROL  
LOGIC  
6-Lead SC70 Package  
8-Lead MSOP Package  
AD7476A/AD7477A/AD7478A  
GND  
APPLICATIONS  
Battery-Powered Systems  
Personal Digital Assistants  
Medical Instruments  
Mobile Communications  
Instrumentation and Control Systems  
Data Acquisition Systems  
High Speed Modems  
Optical Sensors  
PRODUCT HIGHLIGHTS  
GENERAL DESCRIPTION  
1. First 8-/10-/12-bit ADCs in an SC70 package.  
The AD7476A/AD7477A/AD7478A are 12-bit, 10-bit, and 8-bit  
high speed, low power, successive-approximation ADCs, respec-  
tively. The parts operate from a single 2.35 V to 5.25 V power  
supply and feature throughput rates up to 1 MSPS. The parts  
contain a low noise, wide bandwidth track-and-hold amplifier  
that can handle input frequencies in excess of 13 MHz.  
2. High throughput with low power consumption.  
3. Flexible power/serial clock speed management. The conversion  
rate is determined by the serial clock, allowing the conver-  
sion time to be reduced through the serial clock speed increase.  
This allows the average power consumption to be reduced  
when a power-down mode is used while not converting. The  
parts also feature a power-down mode to maximize power  
efficiency at lower throughput rates. Current consumption is  
1 µA max and 50 nA typically when in power-down mode.  
The conversion process and data acquisition are controlled using  
CS and the serial clock, allowing the devices to interface with  
microprocessors or DSPs. The input signal is sampled on the  
falling edge of CS, and the conversion is also initiated at this point.  
There are no pipeline delays associated with the parts.  
4. Reference derived from the power supply.  
The AD7476A/AD7477A/AD7478A use advanced design tech-  
niques to achieve low power dissipation at high throughput rates.  
5. No pipeline delay. The parts feature a standard successive-  
approximation ADC with accurate control of the sampling  
instant via a CS input and once-off conversion control.  
The reference for the part is taken internally from VDD, which  
allows the widest dynamic input range to the ADC. Thus, the  
analog input range for the part is 0 to VDD. The conversion rate is  
determined by the SCLK.  
*Protected by U.S.Patent No. 6,681,332.  
REV. C  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  
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