Datasheet > EVAL-ADF4193EBZ2

EVAL-ADF4193EBZ2

更新时间： 2024-11-27 07:18:47

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
28页	580K
描述
Low Phase Noise, Fast Settling, 6 GHz

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EVAL-ADF4193EBZ2 数据手册

Low Phase Noise, Fast Settling, 6 GHz

PLL Frequency Synthesizer

Data Sheet

ADF4196

FEATURES

GENERAL DESCRIPTION

Fast settling, fractional-N PLL architecture

Single PLL replaces ping-pong synthesizers

The ADF4196 frequency synthesizer can be used to implement

local oscillators (LO) in the upconversion and downconversion

Frequency hop across GSM band in 5 μs with phase settled

within 20 μs

1 degree rms phase error at 4 GHz RF output

Digitally programmable output phase

RF input range up to 6 GHz

3-wire serial interface

On-chip, low noise differential amplifier

Phase noise figure of merit: −216 dBc/Hz

sections of wireless receivers and transmitters. Its architecture is

specifically designed to meet the GSM/EDGE lock time require-

ments for base stations, and the fast settling feature makes the

ADF4196 suitable for pulse Doppler radar applications.

The ADF4196 consists of a low noise, digital phase frequency

detector (PFD) and a precision differential charge pump.

A differential amplifier converts the differential charge pump

output to a single-ended voltage for the external voltage controlled

oscillator (VCO). The sigma-delta (Σ-Δ) based fractional inter-

polator, working with the N divider, allows programmable modulus

fractional-N division. Additionally, the 4-bit reference (R) counter

and on-chip frequency doubler allow selectable reference signal

(REF_IN) frequencies at the PFD input.

APPLICATIONS

GSM/EDGE base stations

PHS base stations

Pulse Doppler radar

Instrumentation and test equipment

Beam-forming/phased array systems

A complete phase-locked loop (PLL) can be implemented if the

synthesizer is used with an external loop filter and a VCO. The

switching architecture ensures that the PLL settles within the

GSM time slot guard period, removing the need for a second

PLL and associated isolation switches. This decreases the cost,

complexity, PCB area, shielding, and characterization found on

previous ping-pong GSM PLL architectures.

FUNCTIONAL BLOCK DIAGRAM

SDV

V 1

V 2

V 3

SET

×2

REFERENCE

SW1

4-BIT R

COUNTER

DIVIDER

PHASE

REF

CHARGE

PUMP

OUT+

FREQUENCY

DETECTOR

DOUBLER

–

OUT–

–

SW2

CMR

HIGH-Z

DGND

LOCK DETECT

DIFFERENTIAL

AMPLIFIER

AIN–

AIN+

–

OUTPUT

MUX

OUT

DIV

OUT

N COUNTER

SW3

FRACTIONAL

INTERPOLATOR

IN+

IN–

CLK

DATA

24-BIT

DATA

FRACTION

REG

MODULUS

REG

INTEGER

REG

ADF4196

GND

Figure 1.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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