Datasheet > EVA-X1610C

EVA-X1610C

更新时间： 2024-11-27 06:58:07

品牌	Logo	应用领域
其他 - ETC		微处理器以太网
页数	文件大小	规格书
2页	196K
描述
16-bit, 75 MHz RISC microprocessor with Ethernet and RS-232 connectivity

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EVA-X1610C 数据手册

EVA-X1610C

16-bit, 75 MHz RISC microprocessor with Ethernet and RS-232 connectivity

Features

• RISC architecture with pipeline technology

• Up to 100 MHz operating frequency

• Fast Ethernet MAC with MII interface

• Dual FIFO UART serial channels

• 80C186 software compatibility

• 16-Bit embedded microcontroller

• Up to 18 programmable I/O pins

• 128-Pin PQFP

Introduction

With the Ethernet protocol becoming the de facto network of choice for ever

•

80C186 software compatibility

more professional, office, industrial, and even home environments, it makes

sense to develop new systems and leverage existing ones to take advantage

of Ethernet connectivity.

Up to 100 MHz operating frequency

SDRAM Control Interface

Advantech’s EVA-X1610C integrates 10/100 Ethernet and RS-232 connectivity

into an economical 80C186-compatible 75MHz RISC microprocessor, putting

the Ethernet within reach of a host of applications.

•

Supports 16-bit data bus width

•

Supports 1Mbit x 16 and 4Mbit x 16 SDRAM devices

Bus Interface

Best Performance-to-Cost

•

One Non-Multiplexed System Bus Interface

Non-multiplexed address and data bus

Supports non-multiplexed address bus A [19:0]

8- or 16-bit external bus dynamic access

Supports max. 512 KB, 8- or 16-bit data width Flash ROM

Multiplexed with SDRAM bus interface

64 K-byte I/O space

The EVA-X1610C is a 16-bit, high performance, RISC architecture

microprocessor with 80C186 compatibility. Additional functions integrated

on the chip are: SDRAM controller, non-multiplexed address bus, interrupt

controller, DMA controller, timers, watchdog timer, FIFO UART serial ports,

programmable I/O (PIO) pins and fast Ethernet MAC (Media Access

Controller).

The advanced internal high-speed local bus architecture significantly increases

overall system performance. And high performance plus high integration

enable the EVA-X1610C to increase functionality while reducing BOM system

costs. This, combined with a royalty-free real-time OS, contributes to its

highly advantageous performance-to-cost ratio. The EVA-X1610C has been

designed to meet the communication requirements of products such as device

servers, medical monitors, industrial machines, scales, security systems,

code scanners, shared IP devices, thermostats, and wireless access points.

Supports memory and I/O devices

1 M-byte memory address space

Supports an independent bus for slower I/O devices

Supports an Independent Bus for I/O Devices

•

Multiplexed address and data

Solution on Chip

External latches are needed to separate address and data bus

16-bit Microprocessor

Only used for I/O devices to prevent throttling the performance of

SDRAM & non-multiplexed system bus

•

RISC architecture with Pipeline Technology

Five-stage pipeline

•

Shares same pins as one of the FIFO UART channels

Static design & Synthesizable design

1 M byte memory address space

64 K byte I/O address space

Dual FIFO UART Serial Channels

System on Chip

Web-enabled”Automation Solutions

Note: All specifications are subject to change without notice.

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