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EPSA23BBHJ-2.375M PDF预览

EPSA23BBHJ-2.375M

更新时间: 2024-12-02 05:14:55
品牌 Logo 应用领域
日蚀 - ECLIPTEK /
页数 文件大小 规格书
10页 795K
描述
CMOS, Spread Spectrum Quartz Crystal Clock Oscillators LVCMOS (CMOS) 3.3Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD) Spread Spectrum Quartz Crystal Clock Oscillators LVCMOS (CMOS) 3.3Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD)

EPSA23BBHJ-2.375M 数据手册

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Ecliptek | EPSA23 Series Oscillator  
http://www.ecliptek.com/oscillators/EPSA23/  
Log On | 714-433-1200 | Email Customer Support  
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EPSA23 Series Oscillator  
Spread Spectrum Quartz Crystal Clock Oscillators LVCMOS (CMOS) 3.3Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount  
(SMD)  
2011/65 +  
168 SVHC  
2015/863  
Revision D 02/27/2015  
ectrical Specifications  
Nominal Frequency  
2.000MHz to 200.000MHz  
Some frequencies within this range may not be available.  
requency Tolerance/Stability  
(Inclusive of all conditions: Frequency Stability over the Operating  
Temperature Range, Supply Voltage Change, Output Load Change,  
First Year Aging at 25°C, Shock, and Vibration)  
±50ppm Maximum  
Operating Temperature Range  
-40°C to +85°C  
upply Voltage (V  
)
DD  
3.3V  
±10%  
DC  
Maximum Supply Voltage  
nput Current  
-0.5V  
to +4.2V  
DC  
DC  
15mA Maximum over Nominal Frequency of 2MHz to 25MHz  
23mA Maximum over Nominal Frequency of 25.000001MHz to 50MHz  
27mA Maximum over Nominal Frequency of 50.000001MHz to 100MHz  
30mA Maximum over Nominal Frequency of 100.000001MHz to  
166MHz  
40mA Maximum over Nominal Frequency of 166.000001MHz to  
200MHz  
Output Voltage Logic High (V  
)
OH  
IOH=-8mA  
90% of V  
Minimum  
Maximum  
DD  
Output Voltage Logic Low (V  
)
IOL=+8mA  
10% of V  
OL  
DD  
uty Cycle  
Measured at 50% of waveform  
50 ±5(%)  
ise Time/Fall Time  
Measured at 10% to 90% of Waveform  
3nSec Maximum  
oad Drive Capability  
Output Logic Type  
15pF Maximum  
CMOS  
Output Control Function  
Tri-State (Disabled Output: High Impedance)  
Power Down (Disabled Output: High Impedance)  
ower Down Input Voltage (Vih and Vil)  
ri-State Input Voltage (Vih and Vil)  
70% of V  
Minimum or No Connection to Enable Output, 30% of V  
DD  
Maximum to Disable Output  
DD  
70% of V  
Minimum or No Connection to Enable Output, 30% of V  
DD  
DD  
Maximum to Disable Output  
ower Down Output Disable Time  
ower Down Output Enable Time  
tandby Current  
100nSec Maximum  
3mSec Maximum  
Unloaded; Pad 1 = Ground  
10µA Maximum (Power Down)  
1 of 10  
28-Jan-2016 2:06 PM  

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