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EPM7512BTC100 PDF预览

EPM7512BTC100

更新时间: 2023-05-15 00:00:00
品牌 Logo 应用领域
阿尔特拉 - ALTERA LTE输入元件可编程逻辑
页数 文件大小 规格书
125页 1051K
描述
EE PLD, CMOS, PQFP100, TQFP-100

EPM7512BTC100 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.6JESD-30 代码:S-PQFP-G100
JESD-609代码:e3长度:14 mm
专用输入次数:4I/O 线路数量:84
端子数量:100组织:4 DEDICATED INPUTS, 84 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH可编程逻辑类型:EE PLD
认证状态:Not Qualified座面最大高度:1.27 mm
最大供电电压:2.625 V最小供电电压:2.375 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm

EPM7512BTC100 数据手册

 浏览型号EPM7512BTC100的Datasheet PDF文件第2页浏览型号EPM7512BTC100的Datasheet PDF文件第3页浏览型号EPM7512BTC100的Datasheet PDF文件第4页浏览型号EPM7512BTC100的Datasheet PDF文件第5页浏览型号EPM7512BTC100的Datasheet PDF文件第6页浏览型号EPM7512BTC100的Datasheet PDF文件第7页 
MAX 7000B  
Programmable Logic  
Device Family  
®
February 2000, ver. 2.0  
Data Sheet  
High-performance 2.5-V CMOS EEPROM-based programmable  
logic devices (PLDs) built on second-generation Multiple Array  
MatriX (MAX®) architecture (see Table 1)  
Features...  
Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V  
MAX 7000A device families  
High-density PLDs ranging from 600 to 10,000 usable gates  
3.5-ns pin-to-pin logic delays with counter frequencies in excess  
of 285.7 MHz  
Preliminary  
Information  
Advanced 2.5-V in-system programmability (ISP)  
Programs through the built-in IEEE Std. 1149.1 Joint Test Action  
Group (JTAG) interface with advanced pin-locking capability  
Enhanced ISP algorithm for faster programming  
ISP_Done bit to ensure complete programming  
Pull-up resistor on I/O pins during in-system programming  
For information on in-system programmable 5.0-V MAX 7000S or 3.3-V  
MAX 7000A devices, see the MAX 7000 Programmable Logic Device Family  
Data Sheet or the MAX 7000A Programmable Logic Device Family Data Sheet.  
f
Table 1. MAX 7000B Device Features  
Note (1)  
Feature  
EPM7032B  
EPM7064B  
EPM7128B  
EPM7256B  
EPM7512B  
Usable gates  
Macrocells  
600  
32  
2
1,250  
64  
2,500  
128  
8
5,000  
256  
16  
10,000  
512  
Logic array blocks  
4
32  
Maximum user I/O  
pins  
36  
68  
100  
164  
212  
t
t
t
t
f
(ns)  
(ns)  
3.5  
2.8  
3.5  
2.7  
4.5  
3.5  
5.0  
3.8  
6.0  
4.3  
PD  
SU  
(ns)  
1.0  
1.0  
1.0  
1.0  
2.0  
FSU  
CO1  
CNT  
(ns)  
1.9  
2.0  
2.5  
2.9  
3.9  
(MHz)  
285.7  
277.8  
212.8  
188.7  
147.1  
Note:  
(1) Contact Altera for up-to-date information on timing information.  
Altera Corporation  
1
A-DS-MAX7000B-01.1  

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