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EPM3032ALC44-7 PDF预览

EPM3032ALC44-7

更新时间: 2024-02-13 09:02:21
品牌 Logo 应用领域
英特尔 - INTEL /
页数 文件大小 规格书
46页 711K
描述
EE PLD, 7.5ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44

EPM3032ALC44-7 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:QCCJ, LDCC44,.7SQReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.24其他特性:YES
最大时钟频率:138.9 MHz系统内可编程:YES
JESD-30 代码:S-PQCC-J44JESD-609代码:e3
JTAG BST:YES长度:16.5862 mm
湿度敏感等级:3专用输入次数:
I/O 线路数量:34宏单元数:32
端子数量:44最高工作温度:70 °C
最低工作温度:组织:0 DEDICATED INPUTS, 34 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC44,.7SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):245电源:2.5/3.3,3.3 V
可编程逻辑类型:EE PLD传播延迟:7.5 ns
认证状态:Not Qualified座面最大高度:4.572 mm
子类别:Programmable Logic Devices最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:16.5862 mmBase Number Matches:1

EPM3032ALC44-7 数据手册

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MAX 3000A  
Programmable Logic  
Device Family  
®
June 2006, ver. 3.5  
Data Sheet  
High–performance, low–cost CMOS EEPROM–based programmable  
logic devices (PLDs) built on a MAX® architecture (see Table 1)  
3.3-V in-system programmability (ISP) through the built–in  
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with  
advanced pin-locking capability  
Features...  
ISP circuitry compliant with IEEE Std. 1532  
Built–in boundary-scan test (BST) circuitry compliant with  
IEEE Std. 1149.1-1990  
Enhanced ISP features:  
Enhanced ISP algorithm for faster programming  
ISP_Done bit to ensure complete programming  
Pull-up resistor on I/O pins during in–system programming  
High–density PLDs ranging from 600 to 10,000 usable gates  
4.5–ns pin–to–pin logic delays with counter frequencies of up to  
227.3 MHz  
MultiVoltTM I/O interface enabling the device core to run at 3.3 V,  
while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic  
levels  
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack  
(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier  
(PLCC), and FineLine BGATM packages  
Hot–socketing support  
Programmable interconnect array (PIA) continuous routing structure  
for fast, predictable performance  
Industrial temperature range  
Table 1. MAX 3000A Device Features  
Feature  
EPM3032A  
EPM3064A  
EPM3128A  
EPM3256A  
EPM3512A  
Usable gates  
Macrocells  
600  
32  
2
1,250  
64  
2,500  
128  
8
5,000  
256  
16  
10,000  
512  
Logic array blocks  
4
32  
Maximum user I/O  
pins  
34  
66  
98  
161  
208  
t
t
t
f
PD (ns)  
4.5  
2.9  
4.5  
2.8  
5.0  
3.3  
7.5  
5.2  
7.5  
5.6  
SU (ns)  
CO1 (ns)  
CNT (MHz)  
3.0  
3.1  
3.4  
4.8  
4.7  
227.3  
222.2  
192.3  
126.6  
116.3  
Altera Corporation  
1
DS-MAX3000A-3.5  

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