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EPF8452ATC100-4 PDF预览

EPF8452ATC100-4

更新时间: 2024-01-27 10:21:56
品牌 Logo 应用领域
阿尔特拉 - ALTERA 可编程逻辑器件
页数 文件大小 规格书
62页 957K
描述
Programmable Logic Device Family

EPF8452ATC100-4 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:LFQFP, TQFP100,.63SQReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.19Is Samacsys:N
其他特性:336 LOGIC ELEMENTSJESD-30 代码:S-PQFP-G100
JESD-609代码:e3长度:14 mm
湿度敏感等级:3专用输入次数:4
I/O 线路数量:78输入次数:68
逻辑单元数量:336输出次数:68
端子数量:100最高工作温度:70 °C
最低工作温度:组织:4 DEDICATED INPUTS, 78 I/O
输出函数:REGISTERED封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:TQFP100,.63SQ
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3,3.3/5,5 V
可编程逻辑类型:LOADABLE PLD认证状态:Not Qualified
座面最大高度:1.27 mm子类别:Field Programmable Gate Arrays
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
Base Number Matches:1

EPF8452ATC100-4 数据手册

 浏览型号EPF8452ATC100-4的Datasheet PDF文件第1页浏览型号EPF8452ATC100-4的Datasheet PDF文件第3页浏览型号EPF8452ATC100-4的Datasheet PDF文件第4页浏览型号EPF8452ATC100-4的Datasheet PDF文件第5页浏览型号EPF8452ATC100-4的Datasheet PDF文件第6页浏览型号EPF8452ATC100-4的Datasheet PDF文件第7页 
FLEX 8000 Programmable Logic Device Family Data Sheet  
JTAG BST circuitry  
Yes  
No  
Yes  
Yes  
No  
Yes  
Peripheral register for fast setup and clock-to-output delay  
Fabricated on an advanced SRAM process  
Available in a variety of packages with 84 to 304 pins (see Table 2)  
Software design support and automatic place-and-route provided by  
the Altera® MAX+PLUS® II development system for Windows-based  
PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM  
RISC System/6000 workstations  
...and More  
Features  
Additional design entry and simulation support provided by EDIF  
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),  
Verilog HDL, VHDL, and other interfaces to popular EDA tools from  
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,  
OrCAD, Synopsys, Synplicity, and Veribest  
Table 2. FLEX 8000 Package Options & I/O Pin Count  
Note (1)  
Device  
84-  
Pin  
100- 144-  
Pin Pin  
160- 160- 192- 208- 225- 232- 240- 280- 304-  
Pin Pin Pin Pin Pin Pin Pin Pin Pin  
PLCC TQFP TQFP PQFP PGA PGA PQFP BGA PGA PQFP PGA RQFP  
EPF8282A  
EPF8282AV  
EPF8452A  
EPF8636A  
EPF8820A  
EPF81188A  
EPF81500A  
68  
78  
78  
68  
68  
68  
120  
118  
120  
120  
136  
152  
136  
152  
148  
112  
152  
184  
184  
181  
208  
208  
Note:  
(1) FLEX 8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad  
flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages.  
Altera’s Flexible Logic Element MatriX (FLEX®) family combines the  
benefits of both erasable programmable logic devices (EPLDs) and field-  
programmable gate arrays (FPGAs). The FLEX 8000 device family is ideal  
for a variety of applications because it combines the fine-grained  
architecture and high register count characteristics of FPGAs with the  
high speed and predictable interconnect delays of EPLDs. Logic is  
implemented in LEs that include compact 4-input look-up tables (LUTs)  
and programmable registers. High performance is provided by a fast,  
continuous network of routing resources.  
General  
Description  
2
Altera Corporation  

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